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evie/android_kernel_oneplus_msm8998

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ARM: CSR: Adding CSR SiRFprimaII board support SiRFprimaII is the latest generation application processor from CSR’s Multifunction SoC product family. Designed around an ARM cortex A9 core, high-speed memory bus, advanced 3D accelerator and full-HD multi-format video decoder, SiRFprimaII is able to meet the needs of complicated applications for modern multifunction devices that require heavy concurrent applications and fluid user experience. Integrated with GPS baseband, analog and PMU, this new platform is designed to provide a cost effective solution for Automotive and Consumer markets. This patch adds the basic support for this SoC and EVB board based on device tree. It is following the ZYNQ of Xilinx in some degree. Signed-off-by: Binghua Duan <Binghua.Duan@csr.com> Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Yuping Luo <Yuping.Luo@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> 2011-07-08 17:40:12 +08:00			`/*`
			`* arch/arm/mach-prima2/include/mach/irqs.h`
			`*`
			`* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.`
			`*`
			`* Licensed under GPLv2 or later.`
			`*/`

			`#ifndef __ASM_ARCH_IRQS_H`
			`#define __ASM_ARCH_IRQS_H`

			`#define SIRFSOC_INTENAL_IRQ_START 0`
ARM: PRIMA2: irq: make prima2 irq can work even we enable GIC for Marco in Marco, we will use GIC. this patch prepares the handle_irq for prima2 to avoid the compiling errors since we want only one defconfig and zImage for both prima2 and marco that means we will need handle_irq for both. Signed-off-by: Baohua Song <Baohua.Song@csr.com> 2012-12-20 19:11:18 +08:00			`#define SIRFSOC_INTENAL_IRQ_END 127`
PINCTRL: SiRF: add GPIO and GPIO irq support in CSR SiRFprimaII In SiRFprimaII, Each GPIO pin can be configured as input or output independently. If a GPIO is configured as input, it can also be enabled as an interrupt source (either edge or level triggered). These pins must be either MUXed as GPIO or other function pads. Signed-off-by: Yuping Luo <yuping.luo@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> 2012-06-19 15:00:05 +08:00			`#define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1)`
ARM: PRIMA2: irq: make prima2 irq can work even we enable GIC for Marco in Marco, we will use GIC. this patch prepares the handle_irq for prima2 to avoid the compiling errors since we want only one defconfig and zImage for both prima2 and marco that means we will need handle_irq for both. Signed-off-by: Baohua Song <Baohua.Song@csr.com> 2012-12-20 19:11:18 +08:00			`#define NR_IRQS 288`
ARM: CSR: Adding CSR SiRFprimaII board support SiRFprimaII is the latest generation application processor from CSR’s Multifunction SoC product family. Designed around an ARM cortex A9 core, high-speed memory bus, advanced 3D accelerator and full-HD multi-format video decoder, SiRFprimaII is able to meet the needs of complicated applications for modern multifunction devices that require heavy concurrent applications and fluid user experience. Integrated with GPS baseband, analog and PMU, this new platform is designed to provide a cost effective solution for Automotive and Consumer markets. This patch adds the basic support for this SoC and EVB board based on device tree. It is following the ZYNQ of Xilinx in some degree. Signed-off-by: Binghua Duan <Binghua.Duan@csr.com> Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Yuping Luo <Yuping.Luo@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> 2011-07-08 17:40:12 +08:00
			`#endif`