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ARM: dts: msm: Add audio fixes for SDM660

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Update internal codec settings for RX/TX devices.
Disable lpass notifier in analog codec driver.
Handle 44.1K support in machine driver to
disable MCLK before request for change in
MCLK frequency.

Change-Id: I5f78f07da46dee0c66e4e374da600e2e5c5d8e21
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
This commit is contained in:
Laxminath Kasam 2017-01-24 18:05:32 +05:30
parent 9335a12bb0
commit 01a680eb49
14 changed files with 66 additions and 79 deletions
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2
arch/arm/boot/dts/qcom/msm-audio.dtsi
View file

@ -827,6 +827,7 @@
qcom,msm-mclk-freq = <9600000>;
qcom,msm-mbhc-hphl-swh = <1>;
qcom,msm-mbhc-gnd-swh = <1>;
qcom,msm-micbias2-ext-cap;
qcom,msm-hs-micbias-type = "external";
qcom,us-euro-gpios = <&us_euro_gpio>;
qcom,cdc-pdm-gpios = <&cdc_pdm_gpios>;
@ -928,7 +929,6 @@
};
clock_audio: audio_ext_clk {
status = "disabled";
compatible = "qcom,audio-ref-clk";
qcom,audio-ref-clk-gpio = <&pm660_gpios 3 0>;
clock-names = "osr_clk";

4
arch/arm/boot/dts/qcom/sdm660-audio.dtsi
View file

@ -167,8 +167,8 @@
cdc_pdm_gpios: cdc_pdm_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_pdm_gpios_active>;
pinctrl-1 = <&cdc_pdm_gpios_sleep>;
pinctrl-0 = <&cdc_pdm_gpios_active &cdc_pdm_2_gpios_active>;
pinctrl-1 = <&cdc_pdm_gpios_sleep &cdc_pdm_2_gpios_sleep>;
qcom,lpi-gpios;
};

6
arch/arm/boot/dts/qcom/sdm660-internal-codec-cdp.dts
View file

@ -24,9 +24,3 @@
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
};
&int_codec {
status = "okay";
qcom,msm-hs-micbias-type = "internal";
qcom,msm-micbias2-ext-cap;
};

1
arch/arm/boot/dts/qcom/sdm660-internal-codec-mtp.dts
View file

@ -27,5 +27,4 @@
&int_codec {
qcom,model = "sdm660-snd-card-mtp";
status = "okay";
};

6
arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-cdp.dts
View file

@ -24,9 +24,3 @@
qcom,board-id = <1 1>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
};
&int_codec {
status = "okay";
qcom,msm-hs-micbias-type = "internal";
qcom,msm-micbias2-ext-cap;
};

6
arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-rcm.dts
View file

@ -24,9 +24,3 @@
qcom,board-id = <21 1>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
};
&int_codec {
status = "okay";
qcom,msm-hs-micbias-type = "internal";
qcom,msm-micbias2-ext-cap;
};

6
arch/arm/boot/dts/qcom/sdm660-internal-codec-rcm.dts
View file

@ -24,9 +24,3 @@
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
};
&int_codec {
status = "okay";
qcom,msm-hs-micbias-type = "internal";
qcom,msm-micbias2-ext-cap;
};

4
arch/arm/boot/dts/qcom/sdm660-internal-codec.dtsi
View file

@ -70,6 +70,10 @@
status = "disabled";
};
&int_codec {
status = "okay";
};
&pmic_analog_codec {
status = "okay";
};

22
arch/arm/boot/dts/qcom/sdm660-lpi.dtsi
View file

@ -157,51 +157,55 @@
cdc_dmic12_gpios_active: dmic12_gpios_active {
mux {
pins = "gpio26", "gpio27";
pins = "gpio26", "gpio28";
function = "func1";
};
config {
pins = "gpio26", "gpio27";
pins = "gpio26", "gpio28";
drive-strength = <8>;
output-high;
};
};
cdc_dmic12_gpios_sleep: dmic12_gpios_sleep {
mux {
pins = "gpio26", "gpio27";
pins = "gpio26", "gpio28";
function = "func1";
};
config {
pins = "gpio26", "gpio27";
pins = "gpio26", "gpio28";
drive-strength = <2>;
bias-disable;
output-low;
};
};
cdc_dmic34_gpios_active: dmic34_gpios_active {
mux {
pins = "gpio28", "gpio29";
pins = "gpio27", "gpio29";
function = "func1";
};
config {
pins = "gpio28", "gpio29";
pins = "gpio27", "gpio29";
drive-strength = <8>;
input-enable;
};
};
cdc_dmic34_gpios_sleep: dmic34_gpios_sleep {
mux {
pins = "gpio28", "gpio29";
pins = "gpio27", "gpio29";
function = "func1";
};
config {
pins = "gpio28", "gpio29";
pins = "gpio27", "gpio29";
drive-strength = <2>;
bias-disable;
pull-down;
input-enable;
};
};
};

21
sound/soc/codecs/sdm660_cdc/msm-analog-cdc.c
View file

@ -94,6 +94,7 @@ static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[];
/* By default enable the internal speaker boost */
static bool spkr_boost_en = true;
static bool initial_boot = true;
static bool is_ssr_en;
static char on_demand_supply_name[][MAX_ON_DEMAND_SUPPLY_NAME_LENGTH] = {
"cdc-vdd-mic-bias",
@ -4052,15 +4053,17 @@ int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
return -ENOMEM;
}
sdm660_cdc_priv->version_entry = version_entry;
sdm660_cdc_priv->audio_ssr_nb.notifier_call =
sdm660_cdc_notifier_service_cb;
ret = audio_notifier_register("pmic_analog_cdc",
AUDIO_NOTIFIER_ADSP_DOMAIN,
&sdm660_cdc_priv->audio_ssr_nb);
if (ret < 0) {
pr_err("%s: Audio notifier register failed ret = %d\n",
__func__, ret);
return ret;
if (is_ssr_en) {
sdm660_cdc_priv->audio_ssr_nb.notifier_call =
sdm660_cdc_notifier_service_cb;
ret = audio_notifier_register("pmic_analog_cdc",
AUDIO_NOTIFIER_ADSP_DOMAIN,
&sdm660_cdc_priv->audio_ssr_nb);
if (ret < 0) {
pr_err("%s: Audio notifier register failed ret = %d\n",
__func__, ret);
return ret;
}
}
return 0;
}

41
sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c
View file

@ -333,21 +333,6 @@ static int msm_dig_cdc_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
return 0;
}
static int msm_dig_cdc_codec_enable_rx_chain(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMD:
snd_soc_update_bits(codec, w->reg,
1 << w->shift, 0x00);
break;
}
return 0;
}
static int msm_dig_cdc_get_iir_enable_audio_mixer(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
@ -809,13 +794,18 @@ static int msm_dig_cdc_codec_enable_dmic(struct snd_soc_dapm_widget *w,
(*dmic_clk_cnt)++;
if (*dmic_clk_cnt == 1) {
snd_soc_update_bits(codec, dmic_clk_reg,
0x0E, 0x02);
0x0E, 0x04);
snd_soc_update_bits(codec, dmic_clk_reg,
dmic_clk_en, dmic_clk_en);
}
snd_soc_update_bits(codec,
MSM89XX_CDC_CORE_TX1_DMIC_CTL + (dmic - 1) * 0x20,
0x07, 0x02);
MSM89XX_CDC_CORE_TX1_DMIC_CTL, 0x07, 0x02);
snd_soc_update_bits(codec,
MSM89XX_CDC_CORE_TX2_DMIC_CTL, 0x07, 0x02);
snd_soc_update_bits(codec,
MSM89XX_CDC_CORE_TX3_DMIC_CTL, 0x07, 0x02);
snd_soc_update_bits(codec,
MSM89XX_CDC_CORE_TX4_DMIC_CTL, 0x07, 0x02);
break;
case SND_SOC_DAPM_POST_PMD:
(*dmic_clk_cnt)--;
@ -1556,18 +1546,9 @@ static const struct snd_soc_dapm_widget msm_dig_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER_E("RX1 CHAIN", SND_SOC_NOPM,
0, 0, NULL, 0,
msm_dig_cdc_codec_enable_rx_chain,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("RX2 CHAIN", SND_SOC_NOPM,
0, 0, NULL, 0,
msm_dig_cdc_codec_enable_rx_chain,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("RX3 CHAIN", SND_SOC_NOPM,
0, 0, NULL, 0,
msm_dig_cdc_codec_enable_rx_chain,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("RX1 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX2 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX3 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_mix1_inp1_mux),

3
sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c
View file

@ -7806,7 +7806,8 @@ static int msm_routing_put_stereo_to_custom_stereo_control(
continue;
if ((port_id != SLIMBUS_0_RX) &&
(port_id != RT_PROXY_PORT_001_RX) &&
(port_id != AFE_PORT_ID_PRIMARY_MI2S_RX))
(port_id != AFE_PORT_ID_PRIMARY_MI2S_RX) &&
(port_id != AFE_PORT_ID_INT4_MI2S_RX))
continue;
for_each_set_bit(i, &msm_bedais[be_index].fe_sessions,

14
sound/soc/msm/qdsp6v2/q6afe.c
View file

@ -5033,6 +5033,20 @@ int afe_validate_port(u16 port_id)
case AFE_PORT_ID_QUATERNARY_TDM_TX_6:
case AFE_PORT_ID_QUATERNARY_TDM_RX_7:
case AFE_PORT_ID_QUATERNARY_TDM_TX_7:
case AFE_PORT_ID_INT0_MI2S_RX:
case AFE_PORT_ID_INT1_MI2S_RX:
case AFE_PORT_ID_INT2_MI2S_RX:
case AFE_PORT_ID_INT3_MI2S_RX:
case AFE_PORT_ID_INT4_MI2S_RX:
case AFE_PORT_ID_INT5_MI2S_RX:
case AFE_PORT_ID_INT6_MI2S_RX:
case AFE_PORT_ID_INT0_MI2S_TX:
case AFE_PORT_ID_INT1_MI2S_TX:
case AFE_PORT_ID_INT2_MI2S_TX:
case AFE_PORT_ID_INT3_MI2S_TX:
case AFE_PORT_ID_INT4_MI2S_TX:
case AFE_PORT_ID_INT5_MI2S_TX:
case AFE_PORT_ID_INT6_MI2S_TX:
{
ret = 0;
break;

9
sound/soc/msm/sdm660-internal.c
View file

@ -730,6 +730,12 @@ static int msm_int_enable_dig_cdc_clk(struct snd_soc_codec *codec,
mutex_lock(&pdata->cdc_int_mclk0_mutex);
if (atomic_read(&pdata->int_mclk0_enabled) == false ||
int_mclk0_freq_chg) {
if (atomic_read(&pdata->int_mclk0_enabled)) {
pdata->digital_cdc_core_clk.enable = 0;
afe_set_lpass_clock_v2(
AFE_PORT_ID_INT0_MI2S_RX,
&pdata->digital_cdc_core_clk);
}
pdata->digital_cdc_core_clk.clk_freq_in_hz =
clk_freq_in_hz;
pdata->digital_cdc_core_clk.enable = 1;
@ -1089,8 +1095,7 @@ static void update_int_mi2s_clk_val(int idx, int stream)
bit_per_sample =
get_int_mi2s_bits_per_sample(int_mi2s_cfg[idx].bit_format);
int_mi2s_clk[idx].clk_freq_in_hz =
(int_mi2s_cfg[idx].sample_rate * int_mi2s_cfg[idx].channels
* bit_per_sample);
(int_mi2s_cfg[idx].sample_rate * 2 * bit_per_sample);
}
static int int_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)