evie/android_kernel_oneplus_msm8998
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drm/nouveau/sw: switch to device pri macros

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:10 +10:00
parent b8ad561e55
commit 01d64afc2e
3 changed files with 19 additions and 16 deletions
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18
drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
View file

@ -51,19 +51,20 @@ gf100_sw_mthd_mp_control(struct nvkm_object *object, u32 mthd,
{ {
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
struct nvkm_sw *sw = (void *)nv_object(chan)->engine; struct nvkm_sw *sw = (void *)nv_object(chan)->engine;
struct nvkm_device *device = sw->engine.subdev.device;
u32 data = *(u32 *)args; u32 data = *(u32 *)args;
switch (mthd) { switch (mthd) {
case 0x600: case 0x600:
nv_wr32(sw, 0x419e00, data); /* MP.PM_UNK000 */ nvkm_wr32(device, 0x419e00, data); /* MP.PM_UNK000 */
break; break;
case 0x644: case 0x644:
if (data & ~0x1ffffe) if (data & ~0x1ffffe)
return -EINVAL; return -EINVAL;
nv_wr32(sw, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */ nvkm_wr32(device, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */
break; break;
case 0x6ac: case 0x6ac:
nv_wr32(sw, 0x419eac, data); /* MP.PM_UNK0AC */ nvkm_wr32(device, 0x419eac, data); /* MP.PM_UNK0AC */
break; break;
default: default:
return -EINVAL; return -EINVAL;
@ -100,13 +101,14 @@ gf100_sw_vblsem_release(struct nvkm_notify *notify)
struct nv50_sw_chan *chan = struct nv50_sw_chan *chan =
container_of(notify, typeof(*chan), vblank.notify[notify->index]); container_of(notify, typeof(*chan), vblank.notify[notify->index]);
struct nvkm_sw *sw = (void *)nv_object(chan)->engine; struct nvkm_sw *sw = (void *)nv_object(chan)->engine;
struct nvkm_bar *bar = nvkm_bar(sw); struct nvkm_device *device = sw->engine.subdev.device;
struct nvkm_bar *bar = device->bar;
nv_wr32(sw, 0x001718, 0x80000000 | chan->vblank.channel); nvkm_wr32(device, 0x001718, 0x80000000 | chan->vblank.channel);
bar->flush(bar); bar->flush(bar);
nv_wr32(sw, 0x06000c, upper_32_bits(chan->vblank.offset)); nvkm_wr32(device, 0x06000c, upper_32_bits(chan->vblank.offset));
nv_wr32(sw, 0x060010, lower_32_bits(chan->vblank.offset)); nvkm_wr32(device, 0x060010, lower_32_bits(chan->vblank.offset));
nv_wr32(sw, 0x060014, chan->vblank.value); nvkm_wr32(device, 0x060014, chan->vblank.value);
return NVKM_NOTIFY_DROP; return NVKM_NOTIFY_DROP;
} }

2
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
View file

@ -97,7 +97,7 @@ nv04_sw_cclass = {
void void
nv04_sw_intr(struct nvkm_subdev *subdev) nv04_sw_intr(struct nvkm_subdev *subdev)
{ {
nv_mask(subdev, 0x000100, 0x80000000, 0x00000000); nvkm_mask(subdev->device, 0x000100, 0x80000000, 0x00000000);
} }
static int static int

15
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
View file

@ -122,18 +122,19 @@ nv50_sw_vblsem_release(struct nvkm_notify *notify)
struct nv50_sw_chan *chan = struct nv50_sw_chan *chan =
container_of(notify, typeof(*chan), vblank.notify[notify->index]); container_of(notify, typeof(*chan), vblank.notify[notify->index]);
struct nvkm_sw *sw = (void *)nv_object(chan)->engine; struct nvkm_sw *sw = (void *)nv_object(chan)->engine;
struct nvkm_bar *bar = nvkm_bar(sw); struct nvkm_device *device = sw->engine.subdev.device;
struct nvkm_bar *bar = device->bar;
nv_wr32(sw, 0x001704, chan->vblank.channel); nvkm_wr32(device, 0x001704, chan->vblank.channel);
nv_wr32(sw, 0x001710, 0x80000000 | chan->vblank.ctxdma); nvkm_wr32(device, 0x001710, 0x80000000 | chan->vblank.ctxdma);
bar->flush(bar); bar->flush(bar);
if (nv_device(sw)->chipset == 0x50) { if (nv_device(sw)->chipset == 0x50) {
nv_wr32(sw, 0x001570, chan->vblank.offset); nvkm_wr32(device, 0x001570, chan->vblank.offset);
nv_wr32(sw, 0x001574, chan->vblank.value); nvkm_wr32(device, 0x001574, chan->vblank.value);
} else { } else {
nv_wr32(sw, 0x060010, chan->vblank.offset); nvkm_wr32(device, 0x060010, chan->vblank.offset);
nv_wr32(sw, 0x060014, chan->vblank.value); nvkm_wr32(device, 0x060014, chan->vblank.value);
} }
return NVKM_NOTIFY_DROP; return NVKM_NOTIFY_DROP;