diff --git a/arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi b/arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi
index b761a06b9e2b..a2c8c89b08a3 100644
--- a/arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi
@@ -39,6 +39,7 @@
 		regulator-name = "gdsc_hlos1_vote_lpass_adsp";
 		reg = <0x17d034 0x4>;
 		qcom,no-status-check-on-disable;
+		qcom,gds-timeout = <500>;
 		status = "disabled";
 	};
 
@@ -47,6 +48,7 @@
 		regulator-name = "gdsc_hlos1_vote_lpass_core";
 		reg = <0x17d038 0x4>;
 		qcom,no-status-check-on-disable;
+		qcom,gds-timeout = <500>;
 		status = "disabled";
 	};
 
@@ -125,6 +127,7 @@
 		      <0x5066008 0x4>;
 		reg-names = "base", "hw_ctrl_addr";
 		qcom,no-status-check-on-disable;
+		qcom,gds-timeout = <500>;
 		status = "disabled";
 	};
 
diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c
index 56b1c2c73dda..e8552f1ebf7e 100644
--- a/drivers/clk/msm/clock-gcc-cobalt.c
+++ b/drivers/clk/msm/clock-gcc-cobalt.c
@@ -1594,6 +1594,7 @@ static struct branch_clk gcc_bimc_gfx_clk = {
 	.cbcr_reg = GCC_BIMC_GFX_CBCR,
 	.has_sibling = 1,
 	.check_enable_bit = true,
+	.no_halt_check_on_disable = true,
 	.base = &virt_base,
 	.c = {
 		.dbg_name = "gcc_bimc_gfx_clk",
@@ -1642,6 +1643,7 @@ static struct branch_clk gcc_gpu_bimc_gfx_clk = {
 	.cbcr_reg = GCC_GPU_BIMC_GFX_CBCR,
 	.has_sibling = 1,
 	.check_enable_bit = true,
+	.no_halt_check_on_disable = true,
 	.base = &virt_base,
 	.c = {
 		.dbg_name = "gcc_gpu_bimc_gfx_clk",
@@ -1664,6 +1666,8 @@ static struct branch_clk gcc_gpu_bimc_gfx_src_clk = {
 static struct branch_clk gcc_gpu_cfg_ahb_clk = {
 	.cbcr_reg = GCC_GPU_CFG_AHB_CBCR,
 	.has_sibling = 1,
+	.check_enable_bit = true,
+	.no_halt_check_on_disable = true,
 	.base = &virt_base,
 	.c = {
 		.dbg_name = "gcc_gpu_cfg_ahb_clk",
diff --git a/drivers/clk/msm/clock-mmss-cobalt.c b/drivers/clk/msm/clock-mmss-cobalt.c
index 4b102dc3f2a2..9182290d1a80 100644
--- a/drivers/clk/msm/clock-mmss-cobalt.c
+++ b/drivers/clk/msm/clock-mmss-cobalt.c
@@ -1095,6 +1095,7 @@ static struct branch_clk mmss_bimc_smmu_ahb_clk = {
 	.cbcr_reg = MMSS_BIMC_SMMU_AHB_CBCR,
 	.has_sibling = 1,
 	.check_enable_bit = true,
+	.no_halt_check_on_disable = true,
 	.base = &virt_base,
 	.c = {
 		.dbg_name = "mmss_bimc_smmu_ahb_clk",
@@ -1107,6 +1108,7 @@ static struct branch_clk mmss_bimc_smmu_axi_clk = {
 	.cbcr_reg = MMSS_BIMC_SMMU_AXI_CBCR,
 	.has_sibling = 1,
 	.check_enable_bit = true,
+	.no_halt_check_on_disable = true,
 	.base = &virt_base,
 	.c = {
 		.dbg_name = "mmss_bimc_smmu_axi_clk",
@@ -2069,6 +2071,7 @@ static struct branch_clk mmss_mnoc_ahb_clk = {
 	.cbcr_reg = MMSS_MNOC_AHB_CBCR,
 	.has_sibling = 0,
 	.check_enable_bit = true,
+	.no_halt_check_on_disable = true,
 	.base = &virt_base,
 	.c = {
 		.dbg_name = "mmss_mnoc_ahb_clk",