staging: comedi: ni_mio_common: refactor m-series stc register handling
For M-Series boards (devpriv->is_m_series), the STC registers need to be remapped. This is currently handled with some big switch statements to convert the STC register offset to the M-Series offset. Some of the registers also need special handling due to differences in the register size on the M-Series boards. Create some lookup tables to handle the remapping of the read and write registers. These are easier to maintain and can contain the register size so that a common function can be used instead of the separate helpers. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
5ccca15567
commit
05dd0c9fcb
1 changed files with 117 additions and 239 deletions
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@ -308,262 +308,140 @@ static uint8_t ni_readb(struct comedi_device *dev, int reg)
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* windowed STC registers to the m series register offsets.
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*/
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static void m_series_stc_writel(struct comedi_device *dev,
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uint32_t data, int reg)
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{
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unsigned offset;
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struct mio_regmap {
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unsigned int mio_reg;
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int size;
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};
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switch (reg) {
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case AI_SC_Load_A_Registers:
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offset = M_Offset_AI_SC_Load_A;
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break;
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case AI_SI_Load_A_Registers:
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offset = M_Offset_AI_SI_Load_A;
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break;
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case AO_BC_Load_A_Register:
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offset = M_Offset_AO_BC_Load_A;
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break;
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case AO_UC_Load_A_Register:
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offset = M_Offset_AO_UC_Load_A;
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break;
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case AO_UI_Load_A_Register:
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offset = M_Offset_AO_UI_Load_A;
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break;
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case G_Load_A_Register(0):
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offset = M_Offset_G0_Load_A;
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break;
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case G_Load_A_Register(1):
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offset = M_Offset_G1_Load_A;
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break;
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case G_Load_B_Register(0):
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offset = M_Offset_G0_Load_B;
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break;
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case G_Load_B_Register(1):
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offset = M_Offset_G1_Load_B;
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break;
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default:
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dev_warn(dev->class_dev,
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"%s: bug! unhandled register=0x%x in switch\n",
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static const struct mio_regmap m_series_stc_write_regmap[] = {
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[Interrupt_A_Ack_Register] = { M_Offset_Interrupt_A_Ack, 2 },
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[Interrupt_B_Ack_Register] = { M_Offset_Interrupt_B_Ack, 2 },
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[AI_Command_2_Register] = { M_Offset_AI_Command_2, 2 },
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[AO_Command_2_Register] = { M_Offset_AO_Command_2, 2 },
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[G_Command_Register(0)] = { M_Offset_G0_Command, 2 },
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[G_Command_Register(1)] = { M_Offset_G1_Command, 2 },
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[AI_Command_1_Register] = { M_Offset_AI_Command_1, 2 },
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[AO_Command_1_Register] = { M_Offset_AO_Command_1, 2 },
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[DIO_Output_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
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/*
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* DIO_Output_Register maps to:
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* { M_Offset_Static_Digital_Output, 4 }
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* { M_Offset_SCXI_Serial_Data_Out, 1 }
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*/
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[DIO_Control_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
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[AI_Mode_1_Register] = { M_Offset_AI_Mode_1, 2 },
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[AI_Mode_2_Register] = { M_Offset_AI_Mode_2, 2 },
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[AI_SI_Load_A_Registers] = { M_Offset_AI_SI_Load_A, 4 },
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[AI_SC_Load_A_Registers] = { M_Offset_AI_SC_Load_A, 4 },
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[AI_SI2_Load_A_Register] = { M_Offset_AI_SI2_Load_A, 4 },
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[AI_SI2_Load_B_Register] = { M_Offset_AI_SI2_Load_B, 4 },
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[G_Mode_Register(0)] = { M_Offset_G0_Mode, 2 },
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[G_Mode_Register(1)] = { M_Offset_G1_Mode, 2 },
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[G_Load_A_Register(0)] = { M_Offset_G0_Load_A, 4 },
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[G_Load_B_Register(0)] = { M_Offset_G0_Load_B, 4 },
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[G_Load_A_Register(1)] = { M_Offset_G1_Load_A, 4 },
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[G_Load_B_Register(1)] = { M_Offset_G1_Load_B, 4 },
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[G_Input_Select_Register(0)] = { M_Offset_G0_Input_Select, 2 },
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[G_Input_Select_Register(1)] = { M_Offset_G1_Input_Select, 2 },
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[AO_Mode_1_Register] = { M_Offset_AO_Mode_1, 2 },
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[AO_Mode_2_Register] = { M_Offset_AO_Mode_2, 2 },
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[AO_UI_Load_A_Register] = { M_Offset_AO_UI_Load_A, 4 },
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[AO_BC_Load_A_Register] = { M_Offset_AO_BC_Load_A, 4 },
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[AO_UC_Load_A_Register] = { M_Offset_AO_UC_Load_A, 4 },
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[Clock_and_FOUT_Register] = { M_Offset_Clock_and_FOUT, 2 },
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[IO_Bidirection_Pin_Register] = { M_Offset_IO_Bidirection_Pin, 2 },
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[RTSI_Trig_Direction_Register] = { M_Offset_RTSI_Trig_Direction, 2 },
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[Interrupt_Control_Register] = { M_Offset_Interrupt_Control, 2 },
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[AI_Output_Control_Register] = { M_Offset_AI_Output_Control, 2 },
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[Analog_Trigger_Etc_Register] = { M_Offset_Analog_Trigger_Etc, 2 },
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[AI_START_STOP_Select_Register] = { M_Offset_AI_START_STOP_Select, 2 },
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[AI_Trigger_Select_Register] = { M_Offset_AI_Trigger_Select, 2 },
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[AO_Start_Select_Register] = { M_Offset_AO_Start_Select, 2 },
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[AO_Trigger_Select_Register] = { M_Offset_AO_Trigger_Select, 2 },
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[G_Autoincrement_Register(0)] = { M_Offset_G0_Autoincrement, 2 },
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[G_Autoincrement_Register(1)] = { M_Offset_G1_Autoincrement, 2 },
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[AO_Mode_3_Register] = { M_Offset_AO_Mode_3, 2 },
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[Joint_Reset_Register] = { M_Offset_Joint_Reset, 2 },
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[Interrupt_A_Enable_Register] = { M_Offset_Interrupt_A_Enable, 2 },
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[Interrupt_B_Enable_Register] = { M_Offset_Interrupt_B_Enable, 2 },
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[AI_Personal_Register] = { M_Offset_AI_Personal, 2 },
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[AO_Personal_Register] = { M_Offset_AO_Personal, 2 },
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[RTSI_Trig_A_Output_Register] = { M_Offset_RTSI_Trig_A_Output, 2 },
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[RTSI_Trig_B_Output_Register] = { M_Offset_RTSI_Trig_B_Output, 2 },
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[Configuration_Memory_Clear] = { M_Offset_Configuration_Memory_Clear,
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2 },
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[ADC_FIFO_Clear] = { M_Offset_AI_FIFO_Clear, 2 },
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[DAC_FIFO_Clear] = { M_Offset_AO_FIFO_Clear, 2 },
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[AO_Output_Control_Register] = { M_Offset_AO_Output_Control, 2 },
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[AI_Mode_3_Register] = { M_Offset_AI_Mode_3, 2 },
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};
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static void m_series_stc_write(struct comedi_device *dev,
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unsigned int data, unsigned int reg)
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{
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const struct mio_regmap *regmap;
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if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
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regmap = &m_series_stc_write_regmap[reg];
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} else {
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dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
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__func__, reg);
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return;
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}
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ni_writel(dev, data, offset);
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}
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static void m_series_stc_writew(struct comedi_device *dev,
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uint16_t data, int reg)
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{
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unsigned offset;
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switch (reg) {
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case ADC_FIFO_Clear:
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offset = M_Offset_AI_FIFO_Clear;
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switch (regmap->size) {
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case 4:
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ni_writel(dev, data, regmap->mio_reg);
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break;
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case AI_Command_1_Register:
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offset = M_Offset_AI_Command_1;
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case 2:
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ni_writew(dev, data, regmap->mio_reg);
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break;
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case AI_Command_2_Register:
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offset = M_Offset_AI_Command_2;
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break;
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case AI_Mode_1_Register:
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offset = M_Offset_AI_Mode_1;
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break;
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case AI_Mode_2_Register:
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offset = M_Offset_AI_Mode_2;
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break;
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case AI_Mode_3_Register:
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offset = M_Offset_AI_Mode_3;
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break;
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case AI_Output_Control_Register:
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offset = M_Offset_AI_Output_Control;
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break;
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case AI_Personal_Register:
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offset = M_Offset_AI_Personal;
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break;
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case AI_SI2_Load_A_Register:
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/* this is a 32 bit register on m series boards */
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ni_writel(dev, data, M_Offset_AI_SI2_Load_A);
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return;
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case AI_SI2_Load_B_Register:
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/* this is a 32 bit register on m series boards */
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ni_writel(dev, data, M_Offset_AI_SI2_Load_B);
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return;
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case AI_START_STOP_Select_Register:
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offset = M_Offset_AI_START_STOP_Select;
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break;
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case AI_Trigger_Select_Register:
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offset = M_Offset_AI_Trigger_Select;
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break;
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case Analog_Trigger_Etc_Register:
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offset = M_Offset_Analog_Trigger_Etc;
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break;
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case AO_Command_1_Register:
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offset = M_Offset_AO_Command_1;
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break;
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case AO_Command_2_Register:
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offset = M_Offset_AO_Command_2;
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break;
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case AO_Mode_1_Register:
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offset = M_Offset_AO_Mode_1;
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break;
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case AO_Mode_2_Register:
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offset = M_Offset_AO_Mode_2;
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break;
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case AO_Mode_3_Register:
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offset = M_Offset_AO_Mode_3;
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break;
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case AO_Output_Control_Register:
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offset = M_Offset_AO_Output_Control;
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break;
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case AO_Personal_Register:
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offset = M_Offset_AO_Personal;
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break;
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case AO_Start_Select_Register:
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offset = M_Offset_AO_Start_Select;
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break;
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case AO_Trigger_Select_Register:
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offset = M_Offset_AO_Trigger_Select;
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break;
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case Clock_and_FOUT_Register:
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offset = M_Offset_Clock_and_FOUT;
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break;
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case Configuration_Memory_Clear:
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offset = M_Offset_Configuration_Memory_Clear;
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break;
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case DAC_FIFO_Clear:
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offset = M_Offset_AO_FIFO_Clear;
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break;
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case DIO_Control_Register:
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dev_dbg(dev->class_dev,
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"%s: FIXME: register 0x%x does not map cleanly on to m-series boards\n",
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__func__, reg);
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return;
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case G_Autoincrement_Register(0):
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offset = M_Offset_G0_Autoincrement;
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break;
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case G_Autoincrement_Register(1):
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offset = M_Offset_G1_Autoincrement;
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break;
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case G_Command_Register(0):
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offset = M_Offset_G0_Command;
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break;
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case G_Command_Register(1):
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offset = M_Offset_G1_Command;
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break;
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case G_Input_Select_Register(0):
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offset = M_Offset_G0_Input_Select;
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break;
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case G_Input_Select_Register(1):
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offset = M_Offset_G1_Input_Select;
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break;
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case G_Mode_Register(0):
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offset = M_Offset_G0_Mode;
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break;
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case G_Mode_Register(1):
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offset = M_Offset_G1_Mode;
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break;
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case Interrupt_A_Ack_Register:
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offset = M_Offset_Interrupt_A_Ack;
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break;
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case Interrupt_A_Enable_Register:
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offset = M_Offset_Interrupt_A_Enable;
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break;
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case Interrupt_B_Ack_Register:
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offset = M_Offset_Interrupt_B_Ack;
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break;
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case Interrupt_B_Enable_Register:
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offset = M_Offset_Interrupt_B_Enable;
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break;
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case Interrupt_Control_Register:
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offset = M_Offset_Interrupt_Control;
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break;
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case IO_Bidirection_Pin_Register:
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offset = M_Offset_IO_Bidirection_Pin;
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break;
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case Joint_Reset_Register:
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offset = M_Offset_Joint_Reset;
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break;
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case RTSI_Trig_A_Output_Register:
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offset = M_Offset_RTSI_Trig_A_Output;
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break;
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case RTSI_Trig_B_Output_Register:
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offset = M_Offset_RTSI_Trig_B_Output;
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break;
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case RTSI_Trig_Direction_Register:
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offset = M_Offset_RTSI_Trig_Direction;
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break;
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/*
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* FIXME: DIO_Output_Register (16 bit reg) is replaced by
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* M_Offset_Static_Digital_Output (32 bit) and
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* M_Offset_SCXI_Serial_Data_Out (8 bit)
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*/
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default:
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dev_warn(dev->class_dev,
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"%s: bug! unhandled register=0x%x in switch\n",
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dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
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__func__, reg);
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return;
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break;
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}
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ni_writew(dev, data, offset);
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}
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static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
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{
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unsigned offset;
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static const struct mio_regmap m_series_stc_read_regmap[] = {
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[AI_Status_1_Register] = { M_Offset_AI_Status_1, 2 },
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[AO_Status_1_Register] = { M_Offset_AO_Status_1, 2 },
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[G_Status_Register] = { M_Offset_G01_Status, 2 },
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[AO_Status_2_Register] = { M_Offset_AO_Status_2, 2 },
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[G_HW_Save_Register(0)] = { M_Offset_G0_HW_Save, 4 },
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[G_HW_Save_Register(1)] = { M_Offset_G1_HW_Save, 4 },
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[G_Save_Register(0)] = { M_Offset_G0_Save, 4 },
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[G_Save_Register(1)] = { M_Offset_G1_Save, 4 },
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[Joint_Status_1_Register] = { M_Offset_Joint_Status_1, 2 },
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[DIO_Serial_Input_Register] = { M_Offset_SCXI_Serial_Data_In, 1 },
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[Joint_Status_2_Register] = { M_Offset_Joint_Status_2, 2 },
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};
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switch (reg) {
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case G_HW_Save_Register(0):
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offset = M_Offset_G0_HW_Save;
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break;
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case G_HW_Save_Register(1):
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offset = M_Offset_G1_HW_Save;
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break;
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case G_Save_Register(0):
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offset = M_Offset_G0_Save;
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break;
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case G_Save_Register(1):
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offset = M_Offset_G1_Save;
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break;
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default:
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dev_warn(dev->class_dev,
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"%s: bug! unhandled register=0x%x in switch\n",
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static unsigned int m_series_stc_read(struct comedi_device *dev,
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unsigned int reg)
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{
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const struct mio_regmap *regmap;
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if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
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regmap = &m_series_stc_read_regmap[reg];
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} else {
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dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
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__func__, reg);
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return 0;
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}
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return ni_readl(dev, offset);
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}
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static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
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{
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unsigned offset;
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switch (reg) {
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case AI_Status_1_Register:
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offset = M_Offset_AI_Status_1;
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break;
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case AO_Status_1_Register:
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offset = M_Offset_AO_Status_1;
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break;
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case AO_Status_2_Register:
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offset = M_Offset_AO_Status_2;
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break;
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case DIO_Serial_Input_Register:
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return ni_readb(dev, M_Offset_SCXI_Serial_Data_In);
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case Joint_Status_1_Register:
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offset = M_Offset_Joint_Status_1;
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break;
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case Joint_Status_2_Register:
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offset = M_Offset_Joint_Status_2;
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break;
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case G_Status_Register:
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offset = M_Offset_G01_Status;
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break;
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switch (regmap->size) {
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case 4:
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return ni_readl(dev, regmap->mio_reg);
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case 2:
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return ni_readw(dev, regmap->mio_reg);
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case 1:
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return ni_readb(dev, regmap->mio_reg);
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default:
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dev_warn(dev->class_dev,
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"%s: bug! unhandled register=0x%x in switch\n",
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dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
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__func__, reg);
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return 0;
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}
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return ni_readw(dev, offset);
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}
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static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
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@ -572,7 +450,7 @@ static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
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unsigned long flags;
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if (devpriv->is_m_series) {
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m_series_stc_writew(dev, data, reg);
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m_series_stc_write(dev, data, reg);
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} else {
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spin_lock_irqsave(&devpriv->window_lock, flags);
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if (!devpriv->mite && reg < 8) {
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@ -590,7 +468,7 @@ static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
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struct ni_private *devpriv = dev->private;
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if (devpriv->is_m_series) {
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m_series_stc_writel(dev, data, reg);
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m_series_stc_write(dev, data, reg);
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} else {
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ni_stc_writew(dev, data >> 16, reg);
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ni_stc_writew(dev, data & 0xffff, reg + 1);
|
||||
|
|
@ -604,7 +482,7 @@ static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
|
|||
uint16_t val;
|
||||
|
||||
if (devpriv->is_m_series) {
|
||||
val = m_series_stc_readw(dev, reg);
|
||||
val = m_series_stc_read(dev, reg);
|
||||
} else {
|
||||
spin_lock_irqsave(&devpriv->window_lock, flags);
|
||||
if (!devpriv->mite && reg < 8) {
|
||||
|
|
@ -624,7 +502,7 @@ static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
|
|||
uint32_t val;
|
||||
|
||||
if (devpriv->is_m_series) {
|
||||
val = m_series_stc_readl(dev, reg);
|
||||
val = m_series_stc_read(dev, reg);
|
||||
} else {
|
||||
val = ni_stc_readw(dev, reg) << 16;
|
||||
val |= ni_stc_readw(dev, reg + 1);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue