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ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC schemes

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This patch
 - refactors gpmc_hwecc_bch_capable()
 - add checks for new platforms like dra7xx, am43xx
 - add checks for OMAP3 SoC, w.r.t. new ECC schemes spawned in following commit:
    commit ac65caf514
    ARM: OMAP2+: cleaned-up DT support of various ECC schemes

Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Pekon Gupta 2014-02-05 18:58:30 +05:30 • committed by Tony Lindgren
parent 24d0bb8861
commit 0611c41934
1 changed files with 20 additions and 11 deletions
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31
arch/arm/mach-omap2/gpmc-nand.c
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@ -45,24 +45,31 @@ static struct platform_device gpmc_nand_device = {
static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
{ {
/* support only OMAP3 class */ /* platforms which support all ECC schemes */
if (!cpu_is_omap34xx() && !soc_is_am33xx()) { if (soc_is_am33xx() || cpu_is_omap44xx() ||
pr_err("BCH ecc is not supported on this CPU\n"); soc_is_omap54xx() || soc_is_dra7xx())
return 1;
/* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
* which require H/W based ECC error detection */
if ((cpu_is_omap34xx() || cpu_is_omap3630()) &&
((ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
(ecc_opt == OMAP_ECC_BCH8_CODE_HW)))
return 0; return 0;
}
/* /*
* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
* and AM33xx derivates. Other chips may be added if confirmed to work. * and AM33xx derivates. Other chips may be added if confirmed to work.
*/ */
if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) &&
(!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) && (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)))
(!soc_is_am33xx())) {
pr_err("BCH 4-bit mode is not supported on this CPU\n");
return 0; return 0;
}
return 1; /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
return 1;
else
return 0;
} }
/* This function will go away once the device-tree convertion is complete */ /* This function will go away once the device-tree convertion is complete */
@ -133,8 +140,10 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
dev_err(dev, "Unsupported NAND ECC scheme selected\n");
return -EINVAL; return -EINVAL;
}
err = platform_device_register(&gpmc_nand_device); err = platform_device_register(&gpmc_nand_device);
if (err < 0) { if (err < 0) {