From 061c93d4f1267fee27767aecaab83119e8dfecce Mon Sep 17 00:00:00 2001 From: Subhash Jadavani Date: Mon, 26 Jan 2015 16:23:57 -0800 Subject: [PATCH] scsi: ufs-qcom: fix device reference clock control handling UFS device reference clock control has moved inside UFS controller register address space for newer Qualcomm chipsets and if we try to do ioremp on the corresponding memory address then it would fail as the same memory address space is already ioremapped. This issue is fixed by removing the requirement of passing reference clock control register address space resource via device tree node for newer chipsets. Change-Id: I8d93f9856d33d3b300bd7994d1dff1d1be84596d Signed-off-by: Subhash Jadavani [subhashj@codeaurora.org: resolved merge conflicts, skipped changes to msmthulium.dtsi] Signed-off-by: Subhash Jadavani --- drivers/scsi/ufs/ufs-qcom.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c index 55a1a6c6c3bb..450b5377051a 100644 --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -1300,24 +1300,28 @@ static int ufs_qcom_init(struct ufs_hba *hba) ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, &host->hw_ver.minor, &host->hw_ver.step); - /* "dev_ref_clk_ctrl_mem" is optional resource */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!res) { - dev_info(dev, "%s: dev_ref_clk_ctrl_mem resource not found\n", - __func__); + /* + * for newer controllers, device reference clock control bit has + * moved inside UFS controller register address space itself. + */ + if (host->hw_ver.major >= 0x02) { + host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; + host->dev_ref_clk_en_mask = BIT(26); } else { - host->dev_ref_clk_ctrl_mmio = devm_ioremap_resource(dev, res); - if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) { - dev_warn(dev, - "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n", - __func__, PTR_ERR(host->dev_ref_clk_ctrl_mmio)); - host->dev_ref_clk_ctrl_mmio = NULL; - } - /* Set the correct mask for the device ref. clock enable bit */ - if (host->hw_ver.major >= 0x02) - host->dev_ref_clk_en_mask = BIT(26); - else + /* "dev_ref_clk_ctrl_mem" is optional resource */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) { + host->dev_ref_clk_ctrl_mmio = + devm_ioremap_resource(dev, res); + if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) { + dev_warn(dev, + "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n", + __func__, + PTR_ERR(host->dev_ref_clk_ctrl_mmio)); + host->dev_ref_clk_ctrl_mmio = NULL; + } host->dev_ref_clk_en_mask = BIT(5); + } } /* update phy revision information before calling phy_init() */