ath9k: Enable Fractional N mode
This patch enables Fractional N mode for all channel if the EEPROM says so, and also fixes the INI only when the device is not a 2 GHz only capable device. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
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fec0de1110
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06d0f0663e
4 changed files with 35 additions and 15 deletions
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@ -466,6 +466,8 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
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return pBase->txMask;
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return pBase->txMask;
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case EEP_RX_MASK:
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case EEP_RX_MASK:
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return pBase->rxMask;
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return pBase->rxMask;
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case EEP_FRAC_N_5G:
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return 0;
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default:
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default:
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return 0;
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return 0;
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}
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}
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@ -1599,6 +1601,11 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
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return pBase->dacHiPwrMode_5G;
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return pBase->dacHiPwrMode_5G;
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else
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else
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return 0;
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return 0;
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case EEP_FRAC_N_5G:
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if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
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return pBase->frac_n_5g;
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else
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return 0;
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default:
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default:
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return 0;
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return 0;
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}
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}
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@ -125,6 +125,7 @@
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#define AR5416_EEP_MINOR_VER_17 0x11
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#define AR5416_EEP_MINOR_VER_17 0x11
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#define AR5416_EEP_MINOR_VER_19 0x13
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#define AR5416_EEP_MINOR_VER_19 0x13
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#define AR5416_EEP_MINOR_VER_20 0x14
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#define AR5416_EEP_MINOR_VER_20 0x14
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#define AR5416_EEP_MINOR_VER_22 0x16
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#define AR5416_NUM_5G_CAL_PIERS 8
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#define AR5416_NUM_5G_CAL_PIERS 8
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#define AR5416_NUM_2G_CAL_PIERS 4
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#define AR5416_NUM_2G_CAL_PIERS 4
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@ -188,6 +189,7 @@ enum eeprom_param {
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EEP_RXGAIN_TYPE,
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EEP_RXGAIN_TYPE,
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EEP_TXGAIN_TYPE,
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EEP_TXGAIN_TYPE,
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EEP_DAC_HPWR_5G,
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EEP_DAC_HPWR_5G,
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EEP_FRAC_N_5G
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};
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};
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enum ar5416_rates {
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enum ar5416_rates {
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@ -232,7 +234,9 @@ struct base_eep_header {
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u8 txGainType;
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u8 txGainType;
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u8 rcChainMask;
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u8 rcChainMask;
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u8 desiredScaleCCK;
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u8 desiredScaleCCK;
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u8 futureBase_3[23];
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u8 power_table_offset;
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u8 frac_n_5g;
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u8 futureBase_3[21];
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} __packed;
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} __packed;
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struct base_eep_header_4k {
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struct base_eep_header_4k {
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@ -823,7 +823,16 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
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if (AR_SREV_9280_20(ah))
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if (AR_SREV_9280_20(ah))
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ath9k_hw_init_txgain_ini(ah);
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ath9k_hw_init_txgain_ini(ah);
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if (ah->hw_version.devid == AR9280_DEVID_PCI) {
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if (!ath9k_hw_fill_cap_info(ah)) {
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DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
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ecode = -EINVAL;
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goto bad;
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}
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if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
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test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
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/* EEPROM Fixup */
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for (i = 0; i < ah->iniModes.ia_rows; i++) {
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for (i = 0; i < ah->iniModes.ia_rows; i++) {
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u32 reg = INI_RA(&ah->iniModes, i, 0);
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u32 reg = INI_RA(&ah->iniModes, i, 0);
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@ -838,13 +847,6 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
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}
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}
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}
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}
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if (!ath9k_hw_fill_cap_info(ah)) {
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DPRINTF(sc, ATH_DBG_RESET,
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"failed ath9k_hw_fill_cap_info\n");
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ecode = -EINVAL;
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goto bad;
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}
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ecode = ath9k_hw_init_macaddr(ah);
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ecode = ath9k_hw_init_macaddr(ah);
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if (ecode != 0) {
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if (ecode != 0) {
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DPRINTF(sc, ATH_DBG_RESET,
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DPRINTF(sc, ATH_DBG_RESET,
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@ -132,20 +132,27 @@ ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
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bMode = 0;
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bMode = 0;
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fracMode = 0;
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fracMode = 0;
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if ((freq % 20) == 0) {
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switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
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aModeRefSel = 3;
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case 0:
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} else if ((freq % 10) == 0) {
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if ((freq % 20) == 0) {
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aModeRefSel = 2;
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aModeRefSel = 3;
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} else {
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} else if ((freq % 10) == 0) {
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aModeRefSel = 2;
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}
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if (aModeRefSel)
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break;
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case 1:
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default:
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aModeRefSel = 0;
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aModeRefSel = 0;
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fracMode = 1;
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fracMode = 1;
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refDivA = 1;
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refDivA = 1;
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channelSel = (freq * 0x8000) / 15;
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channelSel = (freq * 0x8000) / 15;
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REG_RMW_FIELD(ah, AR_AN_SYNTH9,
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REG_RMW_FIELD(ah, AR_AN_SYNTH9,
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AR_AN_SYNTH9_REFDIVA, refDivA);
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AR_AN_SYNTH9_REFDIVA, refDivA);
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}
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}
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if (!fracMode) {
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if (!fracMode) {
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ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
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ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
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channelSel = ndiv & 0x1ff;
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channelSel = ndiv & 0x1ff;
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