perf/x86/intel/uncore: Add Broadwell-DE uncore support
The uncore subsystem for Broadwell-DE is similar to Haswell-EP. There are some differences in pci device IDs, box number and constraints. Please refer to the public document: http://www.intel.com/content/www/us/en/processors/xeon/xeon-d-1500-uncore-performance-monitoring.html Signed-off-by: Kan Liang <kan.liang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1435839172-15114-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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3 changed files with 172 additions and 0 deletions
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@ -911,6 +911,9 @@ static int __init uncore_pci_init(void)
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case 63: /* Haswell-EP */
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case 63: /* Haswell-EP */
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ret = hswep_uncore_pci_init();
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ret = hswep_uncore_pci_init();
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break;
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break;
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case 86: /* BDX-DE */
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ret = bdx_uncore_pci_init();
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break;
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case 42: /* Sandy Bridge */
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case 42: /* Sandy Bridge */
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ret = snb_uncore_pci_init();
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ret = snb_uncore_pci_init();
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break;
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break;
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@ -1229,6 +1232,9 @@ static int __init uncore_cpu_init(void)
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case 63: /* Haswell-EP */
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case 63: /* Haswell-EP */
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hswep_uncore_cpu_init();
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hswep_uncore_cpu_init();
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break;
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break;
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case 86: /* BDX-DE */
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bdx_uncore_cpu_init();
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break;
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default:
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default:
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return 0;
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return 0;
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}
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}
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@ -336,6 +336,8 @@ int ivbep_uncore_pci_init(void);
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void ivbep_uncore_cpu_init(void);
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void ivbep_uncore_cpu_init(void);
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int hswep_uncore_pci_init(void);
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int hswep_uncore_pci_init(void);
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void hswep_uncore_cpu_init(void);
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void hswep_uncore_cpu_init(void);
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int bdx_uncore_pci_init(void);
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void bdx_uncore_cpu_init(void);
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/* perf_event_intel_uncore_nhmex.c */
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/* perf_event_intel_uncore_nhmex.c */
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void nhmex_uncore_cpu_init(void);
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void nhmex_uncore_cpu_init(void);
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@ -2321,3 +2321,167 @@ int hswep_uncore_pci_init(void)
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return 0;
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return 0;
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}
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}
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/* end of Haswell-EP uncore support */
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/* end of Haswell-EP uncore support */
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/* BDX-DE uncore support */
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static struct intel_uncore_type bdx_uncore_ubox = {
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.name = "ubox",
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.num_counters = 2,
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.num_boxes = 1,
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.perf_ctr_bits = 48,
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.fixed_ctr_bits = 48,
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.perf_ctr = HSWEP_U_MSR_PMON_CTR0,
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.event_ctl = HSWEP_U_MSR_PMON_CTL0,
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.event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
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.fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
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.fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
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.num_shared_regs = 1,
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.ops = &ivbep_uncore_msr_ops,
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.format_group = &ivbep_uncore_ubox_format_group,
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};
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static struct event_constraint bdx_uncore_cbox_constraints[] = {
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UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
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EVENT_CONSTRAINT_END
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};
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static struct intel_uncore_type bdx_uncore_cbox = {
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.name = "cbox",
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.num_counters = 4,
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.num_boxes = 8,
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.perf_ctr_bits = 48,
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.event_ctl = HSWEP_C0_MSR_PMON_CTL0,
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.perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
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.event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
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.box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
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.msr_offset = HSWEP_CBO_MSR_OFFSET,
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.num_shared_regs = 1,
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.constraints = bdx_uncore_cbox_constraints,
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.ops = &hswep_uncore_cbox_ops,
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.format_group = &hswep_uncore_cbox_format_group,
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};
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static struct intel_uncore_type *bdx_msr_uncores[] = {
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&bdx_uncore_ubox,
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&bdx_uncore_cbox,
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&hswep_uncore_pcu,
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NULL,
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};
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void bdx_uncore_cpu_init(void)
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{
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if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
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bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
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uncore_msr_uncores = bdx_msr_uncores;
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}
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static struct intel_uncore_type bdx_uncore_ha = {
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.name = "ha",
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.num_counters = 4,
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.num_boxes = 1,
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.perf_ctr_bits = 48,
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SNBEP_UNCORE_PCI_COMMON_INIT(),
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};
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static struct intel_uncore_type bdx_uncore_imc = {
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.name = "imc",
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.num_counters = 5,
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.num_boxes = 2,
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.perf_ctr_bits = 48,
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.fixed_ctr_bits = 48,
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.fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
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.fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
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.event_descs = hswep_uncore_imc_events,
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SNBEP_UNCORE_PCI_COMMON_INIT(),
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};
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static struct intel_uncore_type bdx_uncore_irp = {
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.name = "irp",
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.num_counters = 4,
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.num_boxes = 1,
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.perf_ctr_bits = 48,
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.event_mask = SNBEP_PMON_RAW_EVENT_MASK,
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.box_ctl = SNBEP_PCI_PMON_BOX_CTL,
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.ops = &hswep_uncore_irp_ops,
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.format_group = &snbep_uncore_format_group,
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};
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static struct event_constraint bdx_uncore_r2pcie_constraints[] = {
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UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
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EVENT_CONSTRAINT_END
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};
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static struct intel_uncore_type bdx_uncore_r2pcie = {
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.name = "r2pcie",
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.num_counters = 4,
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.num_boxes = 1,
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.perf_ctr_bits = 48,
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.constraints = bdx_uncore_r2pcie_constraints,
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SNBEP_UNCORE_PCI_COMMON_INIT(),
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};
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enum {
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BDX_PCI_UNCORE_HA,
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BDX_PCI_UNCORE_IMC,
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BDX_PCI_UNCORE_IRP,
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BDX_PCI_UNCORE_R2PCIE,
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};
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static struct intel_uncore_type *bdx_pci_uncores[] = {
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[BDX_PCI_UNCORE_HA] = &bdx_uncore_ha,
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[BDX_PCI_UNCORE_IMC] = &bdx_uncore_imc,
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[BDX_PCI_UNCORE_IRP] = &bdx_uncore_irp,
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[BDX_PCI_UNCORE_R2PCIE] = &bdx_uncore_r2pcie,
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NULL,
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};
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static DEFINE_PCI_DEVICE_TABLE(bdx_uncore_pci_ids) = {
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{ /* Home Agent 0 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f30),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 0),
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},
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{ /* MC0 Channel 0 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0),
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},
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{ /* MC0 Channel 1 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1),
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},
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{ /* IRP */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f39),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IRP, 0),
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},
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{ /* R2PCIe */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f34),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R2PCIE, 0),
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},
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{ /* end: all zeroes */ }
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};
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static struct pci_driver bdx_uncore_pci_driver = {
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.name = "bdx_uncore",
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.id_table = bdx_uncore_pci_ids,
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};
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int bdx_uncore_pci_init(void)
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{
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int ret = snbep_pci2phy_map_init(0x6f1e);
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if (ret)
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return ret;
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uncore_pci_uncores = bdx_pci_uncores;
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uncore_pci_driver = &bdx_uncore_pci_driver;
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return 0;
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}
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/* end of BDX-DE uncore support */
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