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Clean-up for omaps to remove dead code found with cppcheck after

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we've made several SoCs to boot in device tree only mode.
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Merge tag 'omap-for-v3.20/cleanup-pt1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup

Merge "omap clean-up for v3.20" from Tony Lindgren:

Clean-up for omaps to remove dead code found with cppcheck after
we've made several SoCs to boot in device tree only mode.

* tag 'omap-for-v3.20/cleanup-pt1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Remove unused ti81xx platform init code
  ARM: OMAP3+: PRM: remove prm_get_reset_sources declaration from headers
  ARM: OMAP2: CM: remove unused PLL functions
  ARM: OMAP2: clock: remove unused apll code
  ARM: OMAP: dma.c: Remove unused function
  ARM: OMAP1: timer32k.c: Remove unused function
  ARM: OMAP1: irq.c: Remove unused function
  ARM: OMAP2+: omap-pm-noop.c: Remove some unused functions
  ARM: OMAP2+: voltage: Remove some unused functions
  ARM: OMAP2+: powerdomain.c: Remove some unused functions
  ARM: OMAP2+: omap_hwmod.c: Remove some unused functions
  ARM: OMAP2+: dpll44xx.c: Remove unused function
  ARM: OMAP2+: cm33xx.c: Remove some unused functions
  ARM: OMAP2+: clkt2xxx_apll.c: Remove some unused functions

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2015-01-21 16:50:15 -08:00
commit 074450e42f
25 changed files with 3 additions and 1126 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
arch/arm/mach-omap1/irq.c
View file

@ -64,11 +64,6 @@ u32 omap_irq_flags;
static unsigned int irq_bank_count; static unsigned int irq_bank_count;
static struct omap_irq_bank *irq_banks; static struct omap_irq_bank *irq_banks;
static inline unsigned int irq_bank_readl(int bank, int offset)
{
return omap_readl(irq_banks[bank].base_reg + offset);
}
static inline void irq_bank_writel(unsigned long value, int bank, int offset) static inline void irq_bank_writel(unsigned long value, int bank, int offset)
{ {
omap_writel(value, irq_banks[bank].base_reg + offset); omap_writel(value, irq_banks[bank].base_reg + offset);

5
arch/arm/mach-omap1/timer32k.c
View file

@ -91,11 +91,6 @@ static inline void omap_32k_timer_write(int val, int reg)
omap_writew(val, OMAP1_32K_TIMER_BASE + reg); omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
} }
static inline unsigned long omap_32k_timer_read(int reg)
{
return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
}
static inline void omap_32k_timer_start(unsigned long load_val) static inline void omap_32k_timer_start(unsigned long load_val)
{ {
if (!load_val) if (!load_val)

1
arch/arm/mach-omap2/Makefile
View file

@ -181,7 +181,6 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
obj-$(CONFIG_SOC_OMAP2430) += clock2430.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o

6
arch/arm/mach-omap2/cclock3xxx_data.c
View file

@ -3634,10 +3634,6 @@ int __init omap3xxx_clk_init(void)
omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks, omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks)); ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks)); omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
} else if (soc_is_am33xx()) {
cpu_mask = RATE_IN_AM33XX;
} else if (cpu_is_ti814x()) {
cpu_mask = RATE_IN_TI814X;
} else if (cpu_is_omap34xx()) { } else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) { if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1; cpu_mask = RATE_IN_3430ES1;
@ -3681,7 +3677,7 @@ int __init omap3xxx_clk_init(void)
* Lock DPLL5 -- here only until other device init code can * Lock DPLL5 -- here only until other device init code can
* handle this * handle this
*/ */
if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0)) if (omap_rev() >= OMAP3430_REV_ES2_0)
omap3_clk_lock_dpll5(); omap3_clk_lock_dpll5();
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */

142
arch/arm/mach-omap2/clkt2xxx_apll.c
View file

@ -1,142 +0,0 @@
/*
* OMAP2xxx APLL clock control functions
*
* Copyright (C) 2005-2008 Texas Instruments, Inc.
* Copyright (C) 2004-2010 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
* Paul Walmsley
*
* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
* Gordon McNutt and RidgeRun, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#undef DEBUG
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include "clock.h"
#include "clock2xxx.h"
#include "cm2xxx.h"
#include "cm-regbits-24xx.h"
/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
#define EN_APLL_STOPPED 0
#define EN_APLL_LOCKED 3
/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
#define APLLS_CLKIN_19_2MHZ 0
#define APLLS_CLKIN_13MHZ 2
#define APLLS_CLKIN_12MHZ 3
/* Private functions */
/**
* omap2xxx_clk_apll_locked - is the APLL locked?
* @hw: struct clk_hw * of the APLL to check
*
* If the APLL IP block referred to by @hw indicates that it's locked,
* return true; otherwise, return false.
*/
static bool omap2xxx_clk_apll_locked(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 r, apll_mask;
apll_mask = EN_APLL_LOCKED << clk->enable_bit;
r = omap2xxx_cm_get_pll_status();
return ((r & apll_mask) == apll_mask) ? true : false;
}
int omap2_clk_apll96_enable(struct clk_hw *hw)
{
return omap2xxx_cm_apll96_enable();
}
int omap2_clk_apll54_enable(struct clk_hw *hw)
{
return omap2xxx_cm_apll54_enable();
}
static void _apll96_allow_idle(struct clk_hw_omap *clk)
{
omap2xxx_cm_set_apll96_auto_low_power_stop();
}
static void _apll96_deny_idle(struct clk_hw_omap *clk)
{
omap2xxx_cm_set_apll96_disable_autoidle();
}
static void _apll54_allow_idle(struct clk_hw_omap *clk)
{
omap2xxx_cm_set_apll54_auto_low_power_stop();
}
static void _apll54_deny_idle(struct clk_hw_omap *clk)
{
omap2xxx_cm_set_apll54_disable_autoidle();
}
void omap2_clk_apll96_disable(struct clk_hw *hw)
{
omap2xxx_cm_apll96_disable();
}
void omap2_clk_apll54_disable(struct clk_hw *hw)
{
omap2xxx_cm_apll54_disable();
}
unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
unsigned long parent_rate)
{
return (omap2xxx_clk_apll_locked(hw)) ? 54000000 : 0;
}
unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
unsigned long parent_rate)
{
return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0;
}
/* Public data */
const struct clk_hw_omap_ops clkhwops_apll54 = {
.allow_idle = _apll54_allow_idle,
.deny_idle = _apll54_deny_idle,
};
const struct clk_hw_omap_ops clkhwops_apll96 = {
.allow_idle = _apll96_allow_idle,
.deny_idle = _apll96_deny_idle,
};
/* Public functions */
u32 omap2xxx_get_apll_clkin(void)
{
u32 aplls, srate = 0;
aplls = omap2xxx_cm_get_pll_config();
aplls &= OMAP24XX_APLLS_CLKIN_MASK;
aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
if (aplls == APLLS_CLKIN_19_2MHZ)
srate = 19200000;
else if (aplls == APLLS_CLKIN_13MHZ)
srate = 13000000;
else if (aplls == APLLS_CLKIN_12MHZ)
srate = 12000000;
return srate;
}

1
arch/arm/mach-omap2/clock.h
View file

@ -177,7 +177,6 @@ struct clksel {
u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
void omap3_dpll_allow_idle(struct clk_hw_omap *clk); void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
void omap3_dpll_deny_idle(struct clk_hw_omap *clk); void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);

11
arch/arm/mach-omap2/clock2xxx.h
View file

@ -22,12 +22,7 @@ unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
unsigned long parent_rate); unsigned long parent_rate);
void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
unsigned long parent_rate);
unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
unsigned long parent_rate);
unsigned long omap2xxx_clk_get_core_rate(void); unsigned long omap2xxx_clk_get_core_rate(void);
u32 omap2xxx_get_apll_clkin(void);
u32 omap2xxx_get_sysclkdiv(void); u32 omap2xxx_get_sysclkdiv(void);
void omap2xxx_clk_prepare_for_reboot(void); void omap2xxx_clk_prepare_for_reboot(void);
void omap2xxx_clkt_vps_check_bootloader_rates(void); void omap2xxx_clkt_vps_check_bootloader_rates(void);
@ -46,11 +41,5 @@ int omap2430_clk_init(void);
#endif #endif
extern struct clk_hw *dclk_hw; extern struct clk_hw *dclk_hw;
int omap2_enable_osc_ck(struct clk_hw *hw);
void omap2_disable_osc_ck(struct clk_hw *hw);
int omap2_clk_apll96_enable(struct clk_hw *hw);
int omap2_clk_apll54_enable(struct clk_hw *hw);
void omap2_clk_apll96_disable(struct clk_hw *hw);
void omap2_clk_apll54_disable(struct clk_hw *hw);
#endif #endif

10
arch/arm/mach-omap2/cm2xxx.c
View file

@ -370,16 +370,6 @@ u32 omap2xxx_cm_get_core_pll_config(void)
return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
} }
u32 omap2xxx_cm_get_pll_config(void)
{
return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
}
u32 omap2xxx_cm_get_pll_status(void)
{
return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
}
void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm) void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
{ {
u32 tmp; u32 tmp;

2
arch/arm/mach-omap2/cm2xxx.h
View file

@ -60,8 +60,6 @@ extern int omap2xxx_cm_fclks_active(void);
extern int omap2xxx_cm_mpu_retention_allowed(void); extern int omap2xxx_cm_mpu_retention_allowed(void);
extern u32 omap2xxx_cm_get_core_clk_src(void); extern u32 omap2xxx_cm_get_core_clk_src(void);
extern u32 omap2xxx_cm_get_core_pll_config(void); extern u32 omap2xxx_cm_get_core_pll_config(void);
extern u32 omap2xxx_cm_get_pll_config(void);
extern u32 omap2xxx_cm_get_pll_status(void);
extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
u32 mdm); u32 mdm);

21
arch/arm/mach-omap2/cm33xx.c
View file

@ -72,27 +72,6 @@ static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
return v; return v;
} }
static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx)
{
return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx);
}
static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx)
{
return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
}
static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
{
u32 v;
v = am33xx_cm_read_reg(inst, idx);
v &= mask;
v >>= __ffs(mask);
return v;
}
/** /**
* _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
* @inst: CM instance register offset (*_INST macro) * @inst: CM instance register offset (*_INST macro)

20
arch/arm/mach-omap2/dpll44xx.c
View file

@ -36,26 +36,6 @@
/* Static rate multiplier for OMAP4 REGM4XEN clocks */ /* Static rate multiplier for OMAP4 REGM4XEN clocks */
#define OMAP4430_REGM4XEN_MULT 4 #define OMAP4430_REGM4XEN_MULT 4
/* Supported only on OMAP4 */
int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
{
u32 v;
u32 mask;
if (!clk || !clk->clksel_reg)
return -EINVAL;
mask = clk->flags & CLOCK_CLKOUTX2 ?
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
v = omap2_clk_readl(clk, clk->clksel_reg);
v &= mask;
v >>= __ffs(mask);
return v;
}
void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
{ {
u32 v; u32 v;

196
arch/arm/mach-omap2/omap-pm-noop.c
View file

@ -86,200 +86,10 @@ int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
return 0; return 0;
} }
int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
long t)
{
if (!req_dev || !dev || t < -1) {
WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
return -EINVAL;
}
if (t == -1)
pr_debug("OMAP PM: remove max device latency constraint: dev %s\n",
dev_name(dev));
else
pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n",
dev_name(dev), t);
/*
* For current Linux, this needs to map the device to a
* powerdomain, then go through the list of current max lat
* constraints on that powerdomain and find the smallest. If
* the latency constraint has changed, the code should
* recompute the state to enter for the next powerdomain
* state. Conceivably, this code should also determine
* whether to actually disable the device clocks or not,
* depending on how long it takes to re-enable the clocks.
*
* TI CDP code can call constraint_set here.
*/
return 0;
}
int omap_pm_set_max_sdma_lat(struct device *dev, long t)
{
if (!dev || t < -1) {
WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
return -EINVAL;
}
if (t == -1)
pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n",
dev_name(dev));
else
pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n",
dev_name(dev), t);
/*
* For current Linux PM QOS params, this code should scan the
* list of maximum CPU and DMA latencies and select the
* smallest, then set cpu_dma_latency pm_qos_param
* accordingly.
*
* For future Linux PM QOS params, with separate CPU and DMA
* latency params, this code should just set the dma_latency param.
*
* TI CDP code can call constraint_set here.
*/
return 0;
}
int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
{
if (!dev || !c || r < 0) {
WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
return -EINVAL;
}
if (r == 0)
pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n",
dev_name(dev));
else
pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n",
dev_name(dev), r);
/*
* Code in a real implementation should keep track of these
* constraints on the clock, and determine the highest minimum
* clock rate. It should iterate over each OPP and determine
* whether the OPP will result in a clock rate that would
* satisfy this constraint (and any other PM constraint in effect
* at that time). Once it finds the lowest-voltage OPP that
* meets those conditions, it should switch to it, or return
* an error if the code is not capable of doing so.
*/
return 0;
}
/* /*
* DSP Bridge-specific constraints * DSP Bridge-specific constraints
*/ */
const struct omap_opp *omap_pm_dsp_get_opp_table(void)
{
pr_debug("OMAP PM: DSP request for OPP table\n");
/*
* Return DSP frequency table here: The final item in the
* array should have .rate = .opp_id = 0.
*/
return NULL;
}
void omap_pm_dsp_set_min_opp(u8 opp_id)
{
if (opp_id == 0) {
WARN_ON(1);
return;
}
pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id);
/*
*
* For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we
* can just test to see which is higher, the CPU's desired OPP
* ID or the DSP's desired OPP ID, and use whichever is
* highest.
*
* In CDP12.14+, the VDD1 OPP custom clock that controls the DSP
* rate is keyed on MPU speed, not the OPP ID. So we need to
* map the OPP ID to the MPU speed for use with clk_set_rate()
* if it is higher than the current OPP clock rate.
*
*/
}
u8 omap_pm_dsp_get_opp(void)
{
pr_debug("OMAP PM: DSP requests current DSP OPP ID\n");
/*
* For l-o dev tree, call clk_get_rate() on VDD1 OPP clock
*
* CDP12.14+:
* Call clk_get_rate() on the OPP custom clock, map that to an
* OPP ID using the tables defined in board-*.c/chip-*.c files.
*/
return 0;
}
/*
* CPUFreq-originated constraint
*
* In the future, this should be handled by custom OPP clocktype
* functions.
*/
struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void)
{
pr_debug("OMAP PM: CPUFreq request for frequency table\n");
/*
* Return CPUFreq frequency table here: loop over
* all VDD1 clkrates, pull out the mpu_ck frequencies, build
* table
*/
return NULL;
}
void omap_pm_cpu_set_freq(unsigned long f)
{
if (f == 0) {
WARN_ON(1);
return;
}
pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n",
f);
/*
* For l-o dev tree, determine whether MPU freq or DSP OPP id
* freq is higher. Find the OPP ID corresponding to the
* higher frequency. Call clk_round_rate() and clk_set_rate()
* on the OPP custom clock.
*
* CDP should just be able to set the VDD1 OPP clock rate here.
*/
}
unsigned long omap_pm_cpu_get_freq(void)
{
pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n");
/*
* Call clk_get_rate() on the mpu_ck.
*/
return 0;
}
/** /**
* omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled * omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled
@ -363,9 +173,3 @@ int __init omap_pm_if_init(void)
{ {
return 0; return 0;
} }
void omap_pm_if_exit(void)
{
/* Deallocate CPUFreq frequency table here */
}

192
arch/arm/mach-omap2/omap-pm.h
View file

@ -50,14 +50,6 @@ int __init omap_pm_if_early_init(void);
*/ */
int __init omap_pm_if_init(void); int __init omap_pm_if_init(void);
/**
* omap_pm_if_exit - OMAP PM exit code
*
* Exit code; currently unused. The "_if_" is to avoid name
* collisions with the PM idle-loop code.
*/
void omap_pm_if_exit(void);
/* /*
* Device-driver-originated constraints (via board-*.c files, platform_data) * Device-driver-originated constraints (via board-*.c files, platform_data)
*/ */
@ -132,163 +124,6 @@ int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r); int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
/**
* omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
* @req_dev: struct device * requesting the constraint, or NULL if none
* @dev: struct device * to set the constraint one
* @t: maximum device wakeup latency in microseconds
*
* Request that the maximum amount of time necessary for a device @dev
* to become accessible after its clocks are enabled should be no
* greater than @t microseconds. Specifically, this represents the
* time from when a device driver enables device clocks with
* clk_enable(), to when the register reads and writes on the device
* will succeed. This function should be called before clk_disable()
* is called, since the power state transition decision may be made
* during clk_disable().
*
* It is intended that underlying PM code will use this information to
* determine what power state to put the powerdomain enclosing this
* device into.
*
* Multiple calls to omap_pm_set_max_dev_wakeup_lat() will replace the
* previous wakeup latency values for this device. To remove the
* wakeup latency restriction for this device, call with t = -1.
*
* Returns -EINVAL for an invalid argument, -ERANGE if the constraint
* is not satisfiable, or 0 upon success.
*/
int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
long t);
/**
* omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
* @dev: struct device *
* @t: maximum DMA transfer start latency in microseconds
*
* Request that the maximum system DMA transfer start latency for this
* device 'dev' should be no greater than 't' microseconds. "DMA
* transfer start latency" here is defined as the elapsed time from
* when a device (e.g., McBSP) requests that a system DMA transfer
* start or continue, to the time at which data starts to flow into
* that device from the system DMA controller.
*
* It is intended that underlying PM code will use this information to
* determine what power state to put the CORE powerdomain into.
*
* Since system DMA transfers may not involve the MPU, this function
* will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
* so. Similarly, this function will not affect device wakeup latency
* -- use set_max_dev_wakeup_lat() to affect that.
*
* Multiple calls to set_max_sdma_lat() will replace the previous t
* value for this device. To remove the maximum DMA latency for this
* device, call with t = -1.
*
* Returns -EINVAL for an invalid argument, -ERANGE if the constraint
* is not satisfiable, or 0 upon success.
*/
int omap_pm_set_max_sdma_lat(struct device *dev, long t);
/**
* omap_pm_set_min_clk_rate - set minimum clock rate requested by @dev
* @dev: struct device * requesting the constraint
* @clk: struct clk * to set the minimum rate constraint on
* @r: minimum rate in Hz
*
* Request that the minimum clock rate on the device @dev's clk @clk
* be no less than @r Hz.
*
* It is expected that the OMAP PM code will use this information to
* find an OPP or clock setting that will satisfy this clock rate
* constraint, along with any other applicable system constraints on
* the clock rate or corresponding voltage, etc.
*
* omap_pm_set_min_clk_rate() differs from the clock code's
* clk_set_rate() in that it considers other constraints before taking
* any hardware action, and may change a system OPP rather than just a
* clock rate. clk_set_rate() is intended to be a low-level
* interface.
*
* omap_pm_set_min_clk_rate() is easily open to abuse. A better API
* would be something like "omap_pm_set_min_dev_performance()";
* however, there is no easily-generalizable concept of performance
* that applies to all devices. Only a device (and possibly the
* device subsystem) has both the subsystem-specific knowledge, and
* the hardware IP block-specific knowledge, to translate a constraint
* on "touchscreen sampling accuracy" or "number of pixels or polygons
* rendered per second" to a clock rate. This translation can be
* dependent on the hardware IP block's revision, or firmware version,
* and the driver is the only code on the system that has this
* information and can know how to translate that into a clock rate.
*
* The intended use-case for this function is for userspace or other
* kernel code to communicate a particular performance requirement to
* a subsystem; then for the subsystem to communicate that requirement
* to something that is meaningful to the device driver; then for the
* device driver to convert that requirement to a clock rate, and to
* then call omap_pm_set_min_clk_rate().
*
* Users of this function (such as device drivers) should not simply
* call this function with some high clock rate to ensure "high
* performance." Rather, the device driver should take a performance
* constraint from its subsystem, such as "render at least X polygons
* per second," and use some formula or table to convert that into a
* clock rate constraint given the hardware type and hardware
* revision. Device drivers or subsystems should not assume that they
* know how to make a power/performance tradeoff - some device use
* cases may tolerate a lower-fidelity device function for lower power
* consumption; others may demand a higher-fidelity device function,
* no matter what the power consumption.
*
* Multiple calls to omap_pm_set_min_clk_rate() will replace the
* previous rate value for the device @dev. To remove the minimum clock
* rate constraint for the device, call with r = 0.
*
* Returns -EINVAL for an invalid argument, -ERANGE if the constraint
* is not satisfiable, or 0 upon success.
*/
int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r);
/*
* DSP Bridge-specific constraints
*/
/**
* omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
*
* Intended for use by DSPBridge. Returns an array of OPP->DSP clock
* frequency entries. The final item in the array should have .rate =
* .opp_id = 0.
*/
const struct omap_opp *omap_pm_dsp_get_opp_table(void);
/**
* omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
* @opp_id: target DSP OPP ID
*
* Set a minimum OPP ID for the DSP. This is intended to be called
* only from the DSP Bridge MPU-side driver. Unfortunately, the only
* information that code receives from the DSP/BIOS load estimator is the
* target OPP ID; hence, this interface. No return value.
*/
void omap_pm_dsp_set_min_opp(u8 opp_id);
/**
* omap_pm_dsp_get_opp - report the current DSP OPP ID
*
* Report the current OPP for the DSP. Since on OMAP3, the DSP and
* MPU share a single voltage domain, the OPP ID returned back may
* represent a higher DSP speed than the OPP requested via
* omap_pm_dsp_set_min_opp().
*
* Returns the current VDD1 OPP ID, or 0 upon error.
*/
u8 omap_pm_dsp_get_opp(void);
/* /*
* CPUFreq-originated constraint * CPUFreq-originated constraint
* *
@ -296,33 +131,6 @@ u8 omap_pm_dsp_get_opp(void);
* functions. * functions.
*/ */
/**
* omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
*
* Provide a frequency table usable by CPUFreq for the current chip/board.
* Returns a pointer to a struct cpufreq_frequency_table array or NULL
* upon error.
*/
struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
/**
* omap_pm_cpu_set_freq - set the current minimum MPU frequency
* @f: MPU frequency in Hz
*
* Set the current minimum CPU frequency. The actual CPU frequency
* used could end up higher if the DSP requested a higher OPP.
* Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
* return value.
*/
void omap_pm_cpu_set_freq(unsigned long f);
/**
* omap_pm_cpu_get_freq - report the current CPU frequency
*
* Returns the current MPU frequency, or 0 upon error.
*/
unsigned long omap_pm_cpu_get_freq(void);
/* /*
* Device context loss tracking * Device context loss tracking

232
arch/arm/mach-omap2/omap_hwmod.c
View file

@ -3384,91 +3384,6 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
return 0; return 0;
} }
/**
* omap_hwmod_enable_clocks - enable main_clk, all interface clocks
* @oh: struct omap_hwmod *oh
*
* Intended to be called by the omap_device code.
*/
int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
{
unsigned long flags;
spin_lock_irqsave(&oh->_lock, flags);
_enable_clocks(oh);
spin_unlock_irqrestore(&oh->_lock, flags);
return 0;
}
/**
* omap_hwmod_disable_clocks - disable main_clk, all interface clocks
* @oh: struct omap_hwmod *oh
*
* Intended to be called by the omap_device code.
*/
int omap_hwmod_disable_clocks(struct omap_hwmod *oh)
{
unsigned long flags;
spin_lock_irqsave(&oh->_lock, flags);
_disable_clocks(oh);
spin_unlock_irqrestore(&oh->_lock, flags);
return 0;
}
/**
* omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete
* @oh: struct omap_hwmod *oh
*
* Intended to be called by drivers and core code when all posted
* writes to a device must complete before continuing further
* execution (for example, after clearing some device IRQSTATUS
* register bits)
*
* XXX what about targets with multiple OCP threads?
*/
void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
{
BUG_ON(!oh);
if (!oh->class->sysc || !oh->class->sysc->sysc_flags) {
WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n",
oh->name);
return;
}
/*
* Forces posted writes to complete on the OCP thread handling
* register writes
*/
omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
}
/**
* omap_hwmod_reset - reset the hwmod
* @oh: struct omap_hwmod *
*
* Under some conditions, a driver may wish to reset the entire device.
* Called from omap_device code. Returns -EINVAL on error or passes along
* the return value from _reset().
*/
int omap_hwmod_reset(struct omap_hwmod *oh)
{
int r;
unsigned long flags;
if (!oh)
return -EINVAL;
spin_lock_irqsave(&oh->_lock, flags);
r = _reset(oh);
spin_unlock_irqrestore(&oh->_lock, flags);
return r;
}
/* /*
* IP block data retrieval functions * IP block data retrieval functions
*/ */
@ -3723,51 +3638,11 @@ void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh)
return oh->_mpu_rt_va; return oh->_mpu_rt_va;
} }
/**
* omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh
* @oh: struct omap_hwmod *
* @init_oh: struct omap_hwmod * (initiator)
*
* Add a sleep dependency between the initiator @init_oh and @oh.
* Intended to be called by DSP/Bridge code via platform_data for the
* DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge
* code needs to add/del initiator dependencies dynamically
* before/after accessing a device. Returns the return value from
* _add_initiator_dep().
*
* XXX Keep a usecount in the clockdomain code
*/
int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
struct omap_hwmod *init_oh)
{
return _add_initiator_dep(oh, init_oh);
}
/* /*
* XXX what about functions for drivers to save/restore ocp_sysconfig * XXX what about functions for drivers to save/restore ocp_sysconfig
* for context save/restore operations? * for context save/restore operations?
*/ */
/**
* omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh
* @oh: struct omap_hwmod *
* @init_oh: struct omap_hwmod * (initiator)
*
* Remove a sleep dependency between the initiator @init_oh and @oh.
* Intended to be called by DSP/Bridge code via platform_data for the
* DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge
* code needs to add/del initiator dependencies dynamically
* before/after accessing a device. Returns the return value from
* _del_initiator_dep().
*
* XXX Keep a usecount in the clockdomain code
*/
int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
struct omap_hwmod *init_oh)
{
return _del_initiator_dep(oh, init_oh);
}
/** /**
* omap_hwmod_enable_wakeup - allow device to wake up the system * omap_hwmod_enable_wakeup - allow device to wake up the system
* @oh: struct omap_hwmod * * @oh: struct omap_hwmod *
@ -3888,33 +3763,6 @@ int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
return ret; return ret;
} }
/**
* omap_hwmod_read_hardreset - read the HW reset line state of submodules
* contained in the hwmod module
* @oh: struct omap_hwmod *
* @name: name of the reset line to look up and read
*
* Return the current state of the hwmod @oh's reset line named @name:
* returns -EINVAL upon parameter error or if this operation
* is unsupported on the current OMAP; otherwise, passes along the return
* value from _read_hardreset().
*/
int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
{
int ret;
unsigned long flags;
if (!oh)
return -EINVAL;
spin_lock_irqsave(&oh->_lock, flags);
ret = _read_hardreset(oh, name);
spin_unlock_irqrestore(&oh->_lock, flags);
return ret;
}
/** /**
* omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
* @classname: struct omap_hwmod_class name to search for * @classname: struct omap_hwmod_class name to search for
@ -4024,86 +3872,6 @@ int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
return ret; return ret;
} }
/**
* omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup
* @oh: struct omap_hwmod *
*
* Prevent the hwmod @oh from being reset during the setup process.
* Intended for use by board-*.c files on boards with devices that
* cannot tolerate being reset. Must be called before the hwmod has
* been set up. Returns 0 upon success or negative error code upon
* failure.
*/
int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
{
if (!oh)
return -EINVAL;
if (oh->_state != _HWMOD_STATE_REGISTERED) {
pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n",
oh->name);
return -EINVAL;
}
oh->flags |= HWMOD_INIT_NO_RESET;
return 0;
}
/**
* omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ
* @oh: struct omap_hwmod * containing hwmod mux entries
* @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup
* @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup
*
* When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux
* entry number @pad_idx for the hwmod @oh, trigger the interrupt
* service routine for the hwmod's mpu_irqs array index @irq_idx. If
* this function is not called for a given pad_idx, then the ISR
* associated with @oh's first MPU IRQ will be triggered when an I/O
* pad wakeup occurs on that pad. Note that @pad_idx is the index of
* the _dynamic or wakeup_ entry: if there are other entries not
* marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these
* entries are NOT COUNTED in the dynamic pad index. This function
* must be called separately for each pad that requires its interrupt
* to be re-routed this way. Returns -EINVAL if there is an argument
* problem or if @oh does not have hwmod mux entries or MPU IRQs;
* returns -ENOMEM if memory cannot be allocated; or 0 upon success.
*
* XXX This function interface is fragile. Rather than using array
* indexes, which are subject to unpredictable change, it should be
* using hwmod IRQ names, and some other stable key for the hwmod mux
* pad records.
*/
int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
{
int nr_irqs;
might_sleep();
if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 ||
pad_idx >= oh->mux->nr_pads_dynamic)
return -EINVAL;
/* Check the number of available mpu_irqs */
for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++)
;
if (irq_idx >= nr_irqs)
return -EINVAL;
if (!oh->mux->irqs) {
/* XXX What frees this? */
oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic,
GFP_KERNEL);
if (!oh->mux->irqs)
return -ENOMEM;
}
oh->mux->irqs[pad_idx] = irq_idx;
return 0;
}
/** /**
* omap_hwmod_init - initialize the hwmod code * omap_hwmod_init - initialize the hwmod code
* *

16
arch/arm/mach-omap2/omap_hwmod.h
View file

@ -702,13 +702,6 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh);
int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name); int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name); int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
int omap_hwmod_reset(struct omap_hwmod *oh);
void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs); void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs); u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
@ -723,11 +716,6 @@ int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh); void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
struct omap_hwmod *init_oh);
int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
struct omap_hwmod *init_oh);
int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
@ -739,10 +727,6 @@ int omap_hwmod_for_each_by_class(const char *classname,
int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state); int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh); int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
extern void __init omap_hwmod_init(void); extern void __init omap_hwmod_init(void);
const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);

35
arch/arm/mach-omap2/omap_phy_internal.c
View file

@ -152,38 +152,3 @@ void am35x_set_mode(u8 musb_mode)
omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
} }
void ti81xx_musb_phy_power(u8 on)
{
void __iomem *scm_base = NULL;
u32 usbphycfg;
scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K);
if (!scm_base) {
pr_err("system control module ioremap failed\n");
return;
}
usbphycfg = readl_relaxed(scm_base + USBCTRL0);
if (on) {
if (cpu_is_ti816x()) {
usbphycfg |= TI816X_USBPHY0_NORMAL_MODE;
usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC;
} else if (cpu_is_ti814x()) {
usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN
| USBPHY_DPINPUT | USBPHY_DMINPUT);
usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN
| USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL);
}
} else {
if (cpu_is_ti816x())
usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE;
else if (cpu_is_ti814x())
usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
}
writel_relaxed(usbphycfg, scm_base + USBCTRL0);
iounmap(scm_base);
}

82
arch/arm/mach-omap2/powerdomain.c
View file

@ -115,7 +115,6 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
} }
pwrdm->voltdm.ptr = voltdm; pwrdm->voltdm.ptr = voltdm;
INIT_LIST_HEAD(&pwrdm->voltdm_node); INIT_LIST_HEAD(&pwrdm->voltdm_node);
voltdm_add_pwrdm(voltdm, pwrdm);
skip_voltdm: skip_voltdm:
spin_lock_init(&pwrdm->_lock); spin_lock_init(&pwrdm->_lock);
@ -483,87 +482,6 @@ pac_exit:
return ret; return ret;
} }
/**
* pwrdm_del_clkdm - remove a clockdomain from a powerdomain
* @pwrdm: struct powerdomain * to add the clockdomain to
* @clkdm: struct clockdomain * to associate with a powerdomain
*
* Dissociate the clockdomain @clkdm from the powerdomain
* @pwrdm. Returns -EINVAL if presented with invalid pointers; -ENOENT
* if @clkdm was not associated with the powerdomain, or 0 upon
* success.
*/
int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
{
int ret = -EINVAL;
int i;
if (!pwrdm || !clkdm)
return -EINVAL;
pr_debug("powerdomain: %s: dissociating clockdomain %s\n",
pwrdm->name, clkdm->name);
for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
if (pwrdm->pwrdm_clkdms[i] == clkdm)
break;
if (i == PWRDM_MAX_CLKDMS) {
pr_debug("powerdomain: %s: clkdm %s not associated?!\n",
pwrdm->name, clkdm->name);
ret = -ENOENT;
goto pdc_exit;
}
pwrdm->pwrdm_clkdms[i] = NULL;
ret = 0;
pdc_exit:
return ret;
}
/**
* pwrdm_for_each_clkdm - call function on each clkdm in a pwrdm
* @pwrdm: struct powerdomain * to iterate over
* @fn: callback function *
*
* Call the supplied function @fn for each clockdomain in the powerdomain
* @pwrdm. The callback function can return anything but 0 to bail
* out early from the iterator. Returns -EINVAL if presented with
* invalid pointers; or passes along the last return value of the
* callback function, which should be 0 for success or anything else
* to indicate failure.
*/
int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
int (*fn)(struct powerdomain *pwrdm,
struct clockdomain *clkdm))
{
int ret = 0;
int i;
if (!fn)
return -EINVAL;
for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++)
if (pwrdm->pwrdm_clkdms[i])
ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
return ret;
}
/**
* pwrdm_get_voltdm - return a ptr to the voltdm that this pwrdm resides in
* @pwrdm: struct powerdomain *
*
* Return a pointer to the struct voltageomain that the specified powerdomain
* @pwrdm exists in.
*/
struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm)
{
return pwrdm->voltdm.ptr;
}
/** /**
* pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
* @pwrdm: struct powerdomain * * @pwrdm: struct powerdomain *

5
arch/arm/mach-omap2/powerdomain.h
View file

@ -212,11 +212,6 @@ int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
void *user); void *user);
int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
int (*fn)(struct powerdomain *pwrdm,
struct clockdomain *clkdm));
struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);

1
arch/arm/mach-omap2/prm3xxx.h
View file

@ -145,7 +145,6 @@ extern void omap3_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
extern int __init omap3xxx_prm_init(void); extern int __init omap3xxx_prm_init(void);
extern u32 omap3xxx_prm_get_reset_sources(void);
int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits); int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
void omap3xxx_prm_iva_idle(void); void omap3xxx_prm_iva_idle(void);
void omap3_prm_reset_modem(void); void omap3_prm_reset_modem(void);

1
arch/arm/mach-omap2/prm44xx_54xx.h
View file

@ -39,7 +39,6 @@ extern void omap4_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
extern int __init omap44xx_prm_init(void); extern int __init omap44xx_prm_init(void);
extern u32 omap44xx_prm_get_reset_sources(void);
#endif #endif

12
arch/arm/mach-omap2/usb-musb.c
View file

@ -82,16 +82,8 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
musb_plat.mode = board_data->mode; musb_plat.mode = board_data->mode;
musb_plat.extvbus = board_data->extvbus; musb_plat.extvbus = board_data->extvbus;
if (soc_is_am35xx()) { oh_name = "usb_otg_hs";
oh_name = "am35x_otg_hs"; name = "musb-omap2430";
name = "musb-am35x";
} else if (cpu_is_ti81xx()) {
oh_name = "usb_otg_hs";
name = "musb-ti81xx";
} else {
oh_name = "usb_otg_hs";
name = "musb-omap2430";
}
oh = omap_hwmod_lookup(oh_name); oh = omap_hwmod_lookup(oh_name);
if (WARN(!oh, "%s: could not find omap_hwmod for %s\n", if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",

2
arch/arm/mach-omap2/usb.h
View file

@ -68,5 +68,3 @@ extern void am35x_musb_reset(void);
extern void am35x_musb_phy_power(u8 on); extern void am35x_musb_phy_power(u8 on);
extern void am35x_musb_clear_irq(void); extern void am35x_musb_clear_irq(void);
extern void am35x_set_mode(u8 musb_mode); extern void am35x_set_mode(u8 musb_mode);
extern void ti81xx_musb_phy_power(u8 on);

110
arch/arm/mach-omap2/voltage.c
View file

@ -223,37 +223,6 @@ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
return 0; return 0;
} }
/**
* omap_change_voltscale_method() - API to change the voltage scaling method.
* @voltdm: pointer to the VDD whose voltage scaling method
* has to be changed.
* @voltscale_method: the method to be used for voltage scaling.
*
* This API can be used by the board files to change the method of voltage
* scaling between vpforceupdate and vcbypass. The parameter values are
* defined in voltage.h
*/
void omap_change_voltscale_method(struct voltagedomain *voltdm,
int voltscale_method)
{
if (!voltdm || IS_ERR(voltdm)) {
pr_warn("%s: VDD specified does not exist!\n", __func__);
return;
}
switch (voltscale_method) {
case VOLTSCALE_VPFORCEUPDATE:
voltdm->scale = omap_vp_forceupdate_scale;
return;
case VOLTSCALE_VCBYPASS:
voltdm->scale = omap_vc_bypass_scale;
return;
default:
pr_warn("%s: Trying to change the method of voltage scaling to an unsupported one!\n",
__func__);
}
}
/** /**
* omap_voltage_late_init() - Init the various voltage parameters * omap_voltage_late_init() - Init the various voltage parameters
* *
@ -316,90 +285,11 @@ static struct voltagedomain *_voltdm_lookup(const char *name)
return voltdm; return voltdm;
} }
/**
* voltdm_add_pwrdm - add a powerdomain to a voltagedomain
* @voltdm: struct voltagedomain * to add the powerdomain to
* @pwrdm: struct powerdomain * to associate with a voltagedomain
*
* Associate the powerdomain @pwrdm with a voltagedomain @voltdm. This
* enables the use of voltdm_for_each_pwrdm(). Returns -EINVAL if
* presented with invalid pointers; -ENOMEM if memory could not be allocated;
* or 0 upon success.
*/
int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm)
{
if (!voltdm || !pwrdm)
return -EINVAL;
pr_debug("voltagedomain: %s: associating powerdomain %s\n",
voltdm->name, pwrdm->name);
list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list);
return 0;
}
/**
* voltdm_for_each_pwrdm - call function for each pwrdm in a voltdm
* @voltdm: struct voltagedomain * to iterate over
* @fn: callback function *
*
* Call the supplied function @fn for each powerdomain in the
* voltagedomain @voltdm. Returns -EINVAL if presented with invalid
* pointers; or passes along the last return value of the callback
* function, which should be 0 for success or anything else to
* indicate failure.
*/
int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
int (*fn)(struct voltagedomain *voltdm,
struct powerdomain *pwrdm))
{
struct powerdomain *pwrdm;
int ret = 0;
if (!fn)
return -EINVAL;
list_for_each_entry(pwrdm, &voltdm->pwrdm_list, voltdm_node)
ret = (*fn)(voltdm, pwrdm);
return ret;
}
/**
* voltdm_for_each - call function on each registered voltagedomain
* @fn: callback function *
*
* Call the supplied function @fn for each registered voltagedomain.
* The callback function @fn can return anything but 0 to bail out
* early from the iterator. Returns the last return value of the
* callback function, which should be 0 for success or anything else
* to indicate failure; or -EINVAL if the function pointer is null.
*/
int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
void *user)
{
struct voltagedomain *temp_voltdm;
int ret = 0;
if (!fn)
return -EINVAL;
list_for_each_entry(temp_voltdm, &voltdm_list, node) {
ret = (*fn)(temp_voltdm, user);
if (ret)
break;
}
return ret;
}
static int _voltdm_register(struct voltagedomain *voltdm) static int _voltdm_register(struct voltagedomain *voltdm)
{ {
if (!voltdm || !voltdm->name) if (!voltdm || !voltdm->name)
return -EINVAL; return -EINVAL;
INIT_LIST_HEAD(&voltdm->pwrdm_list);
list_add(&voltdm->node, &voltdm_list); list_add(&voltdm->node, &voltdm_list);
pr_debug("voltagedomain: registered %s\n", voltdm->name); pr_debug("voltagedomain: registered %s\n", voltdm->name);

13
arch/arm/mach-omap2/voltage.h
View file

@ -23,10 +23,6 @@
struct powerdomain; struct powerdomain;
/* XXX document */
#define VOLTSCALE_VPFORCEUPDATE 1
#define VOLTSCALE_VCBYPASS 2
/* /*
* OMAP3 GENERIC setup times. Revisit to see if these needs to be * OMAP3 GENERIC setup times. Revisit to see if these needs to be
* passed from board or PMIC file * passed from board or PMIC file
@ -55,7 +51,6 @@ struct omap_vfsm_instance {
* @name: Name of the voltage domain which can be used as a unique identifier. * @name: Name of the voltage domain which can be used as a unique identifier.
* @scalable: Whether or not this voltage domain is scalable * @scalable: Whether or not this voltage domain is scalable
* @node: list_head linking all voltage domains * @node: list_head linking all voltage domains
* @pwrdm_list: list_head linking all powerdomains in this voltagedomain
* @vc: pointer to VC channel associated with this voltagedomain * @vc: pointer to VC channel associated with this voltagedomain
* @vp: pointer to VP associated with this voltagedomain * @vp: pointer to VP associated with this voltagedomain
* @read: read a VC/VP register * @read: read a VC/VP register
@ -71,7 +66,6 @@ struct voltagedomain {
char *name; char *name;
bool scalable; bool scalable;
struct list_head node; struct list_head node;
struct list_head pwrdm_list;
struct omap_vc_channel *vc; struct omap_vc_channel *vc;
const struct omap_vfsm_instance *vfsm; const struct omap_vfsm_instance *vfsm;
struct omap_vp_instance *vp; struct omap_vp_instance *vp;
@ -163,8 +157,6 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
unsigned long volt); unsigned long volt);
int omap_voltage_register_pmic(struct voltagedomain *voltdm, int omap_voltage_register_pmic(struct voltagedomain *voltdm,
struct omap_voltdm_pmic *pmic); struct omap_voltdm_pmic *pmic);
void omap_change_voltscale_method(struct voltagedomain *voltdm,
int voltscale_method);
int omap_voltage_late_init(void); int omap_voltage_late_init(void);
extern void omap2xxx_voltagedomains_init(void); extern void omap2xxx_voltagedomains_init(void);
@ -175,11 +167,6 @@ extern void omap54xx_voltagedomains_init(void);
struct voltagedomain *voltdm_lookup(const char *name); struct voltagedomain *voltdm_lookup(const char *name);
void voltdm_init(struct voltagedomain **voltdm_list); void voltdm_init(struct voltagedomain **voltdm_list);
int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm); int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm);
int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
void *user);
int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
int (*fn)(struct voltagedomain *voltdm,
struct powerdomain *pwrdm));
int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt); int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
void voltdm_reset(struct voltagedomain *voltdm); void voltdm_reset(struct voltagedomain *voltdm);
unsigned long voltdm_get_voltage(struct voltagedomain *voltdm); unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);

8
arch/arm/plat-omap/dma.c
View file

@ -151,14 +151,6 @@ static int omap_dma_in_1510_mode(void)
#endif #endif
#ifdef CONFIG_ARCH_OMAP1 #ifdef CONFIG_ARCH_OMAP1
static inline int get_gdma_dev(int req)
{
u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
int shift = ((req - 1) % 5) * 6;
return ((omap_readl(reg) >> shift) & 0x3f) + 1;
}
static inline void set_gdma_dev(int req, int dev) static inline void set_gdma_dev(int req, int dev)
{ {
u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;