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drm/i915: Limit CHV max cdclk

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Limit CHV maximum cdclk to 320MHz.

v2: Rebase to the latest
v3: Clean up of if-else tree

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Mika Kahola 2015-06-12 10:11:32 +03:00 • committed by Daniel Vetter
parent d8514d6306
commit 0904deaf4e
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/i915/intel_display.c
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@ -5271,6 +5271,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
dev_priv->max_cdclk_freq = 540000; dev_priv->max_cdclk_freq = 540000;
else else
dev_priv->max_cdclk_freq = 675000; dev_priv->max_cdclk_freq = 675000;
} else if (IS_CHERRYVIEW(dev)) {
dev_priv->max_cdclk_freq = 320000;
} else if (IS_VALLEYVIEW(dev)) { } else if (IS_VALLEYVIEW(dev)) {
dev_priv->max_cdclk_freq = 400000; dev_priv->max_cdclk_freq = 400000;
} else { } else {