Merge "clk: qcom: Add support for debugfs support"
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commit
0956d6dd49
4 changed files with 159 additions and 1 deletions
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@ -562,12 +562,48 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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return clamp(rate, min_freq, max_freq);
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}
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static void clk_alpha_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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int size, i, val;
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static struct clk_register_data data[] = {
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{"PLL_MODE", 0x0},
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{"PLL_L_VAL", 0x4},
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{"PLL_ALPHA_VAL", 0x8},
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{"PLL_ALPHA_VAL_U", 0xC},
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{"PLL_USER_CTL", 0x10},
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{"PLL_CONFIG_CTL", 0x18},
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};
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static struct clk_register_data data1[] = {
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{"APSS_PLL_VOTE", 0x0},
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};
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size = ARRAY_SIZE(data);
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for (i = 0; i < size; i++) {
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regmap_read(pll->clkr.regmap, pll->offset + data[i].offset,
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&val);
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seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
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}
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regmap_read(pll->clkr.regmap, pll->offset + data[0].offset, &val);
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if (val & PLL_FSM_ENA) {
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regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
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data1[0].offset, &val);
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seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val);
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}
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}
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const struct clk_ops clk_alpha_pll_ops = {
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.enable = clk_alpha_pll_enable,
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.disable = clk_alpha_pll_disable,
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.recalc_rate = clk_alpha_pll_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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.set_rate = clk_alpha_pll_set_rate,
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.list_registers = clk_alpha_pll_list_registers,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
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@ -577,6 +613,7 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
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.recalc_rate = clk_alpha_pll_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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.set_rate = clk_alpha_pll_set_rate,
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.list_registers = clk_alpha_pll_list_registers,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
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@ -16,10 +16,12 @@
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "clk-branch.h"
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#include "clk-regmap.h"
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static bool clk_branch_in_hwcg_mode(const struct clk_branch *br)
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{
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@ -181,6 +183,43 @@ const struct clk_ops clk_branch_ops = {
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};
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EXPORT_SYMBOL_GPL(clk_branch_ops);
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static void clk_branch2_list_registers(struct seq_file *f, struct clk_hw *hw)
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{
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struct clk_branch *br = to_clk_branch(hw);
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struct clk_regmap *rclk = to_clk_regmap(hw);
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int size, i, val;
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static struct clk_register_data data[] = {
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{"CBCR", 0x0},
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};
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static struct clk_register_data data1[] = {
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{"APSS_VOTE", 0x0},
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{"APSS_SLEEP_VOTE", 0x4},
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};
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size = ARRAY_SIZE(data);
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for (i = 0; i < size; i++) {
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regmap_read(br->clkr.regmap, br->halt_reg + data[i].offset,
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&val);
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seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
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}
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if ((br->halt_check & BRANCH_HALT_VOTED) &&
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!(br->halt_check & BRANCH_VOTED)) {
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if (rclk->enable_reg) {
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size = ARRAY_SIZE(data1);
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for (i = 0; i < size; i++) {
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regmap_read(br->clkr.regmap, rclk->enable_reg +
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data1[i].offset, &val);
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seq_printf(f, "%20s: 0x%.8x\n",
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data1[i].name, val);
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}
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}
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}
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}
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static int clk_branch2_enable(struct clk_hw *hw)
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{
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return clk_branch_toggle(hw, true, clk_branch2_check_halt);
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@ -196,6 +235,7 @@ const struct clk_ops clk_branch2_ops = {
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.disable = clk_branch2_disable,
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.is_enabled = clk_is_enabled_regmap,
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.set_flags = clk_branch_set_flags,
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.list_registers = clk_branch2_list_registers,
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};
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EXPORT_SYMBOL_GPL(clk_branch2_ops);
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@ -228,10 +268,29 @@ static void clk_gate2_disable(struct clk_hw *hw)
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clk_gate_toggle(hw, false);
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}
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static void clk_gate2_list_registers(struct seq_file *f, struct clk_hw *hw)
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{
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struct clk_gate2 *gt = to_clk_gate2(hw);
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int size, i, val;
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static struct clk_register_data data[] = {
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{"EN_REG", 0x0},
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};
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size = ARRAY_SIZE(data);
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for (i = 0; i < size; i++) {
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regmap_read(gt->clkr.regmap, gt->clkr.enable_reg +
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data[i].offset, &val);
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seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
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}
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}
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const struct clk_ops clk_gate2_ops = {
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.enable = clk_gate2_enable,
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.disable = clk_gate2_disable,
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.is_enabled = clk_is_enabled_regmap,
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.list_registers = clk_gate2_list_registers,
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};
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EXPORT_SYMBOL_GPL(clk_gate2_ops);
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@ -317,6 +317,53 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
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return update_config(rcg);
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}
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static void clk_rcg2_list_registers(struct seq_file *f, struct clk_hw *hw)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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int i = 0, size = 0, val;
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static struct clk_register_data data[] = {
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{"CMD_RCGR", 0x0},
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{"CFG_RCGR", 0x4},
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};
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static struct clk_register_data data1[] = {
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{"CMD_RCGR", 0x0},
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{"CFG_RCGR", 0x4},
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{"M_VAL", 0x8},
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{"N_VAL", 0xC},
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{"D_VAL", 0x10},
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};
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if (rcg->mnd_width) {
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size = ARRAY_SIZE(data1);
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for (i = 0; i < size; i++) {
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regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +
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data1[i].offset), &val);
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seq_printf(f, "%20s: 0x%.8x\n", data1[i].name, val);
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}
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} else {
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size = ARRAY_SIZE(data);
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for (i = 0; i < size; i++) {
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regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +
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data[i].offset), &val);
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seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
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}
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}
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}
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/* Return the nth supported frequency for a given clock. */
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static long clk_rcg2_list_rate(struct clk_hw *hw, unsigned n,
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unsigned long fmax)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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if (!rcg->freq_tbl)
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return -ENXIO;
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return (rcg->freq_tbl + n)->freq;
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}
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static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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@ -351,6 +398,8 @@ const struct clk_ops clk_rcg2_ops = {
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.determine_rate = clk_rcg2_determine_rate,
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.set_rate = clk_rcg2_set_rate,
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.set_rate_and_parent = clk_rcg2_set_rate_and_parent,
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.list_rate = clk_rcg2_list_rate,
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.list_registers = clk_rcg2_list_registers,
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};
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EXPORT_SYMBOL_GPL(clk_rcg2_ops);
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@ -557,6 +606,7 @@ const struct clk_ops clk_edp_pixel_ops = {
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.set_rate = clk_edp_pixel_set_rate,
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.set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
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.determine_rate = clk_edp_pixel_determine_rate,
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.list_registers = clk_rcg2_list_registers,
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};
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EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
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@ -615,6 +665,7 @@ const struct clk_ops clk_byte_ops = {
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.set_rate = clk_byte_set_rate,
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.set_rate_and_parent = clk_byte_set_rate_and_parent,
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.determine_rate = clk_byte_determine_rate,
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.list_registers = clk_rcg2_list_registers,
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};
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EXPORT_SYMBOL_GPL(clk_byte_ops);
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@ -685,6 +736,7 @@ const struct clk_ops clk_byte2_ops = {
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.set_rate = clk_byte2_set_rate,
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.set_rate_and_parent = clk_byte2_set_rate_and_parent,
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.determine_rate = clk_byte2_determine_rate,
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.list_registers = clk_rcg2_list_registers,
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};
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EXPORT_SYMBOL_GPL(clk_byte2_ops);
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@ -775,6 +827,7 @@ const struct clk_ops clk_pixel_ops = {
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.set_rate = clk_pixel_set_rate,
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.set_rate_and_parent = clk_pixel_set_rate_and_parent,
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.determine_rate = clk_pixel_determine_rate,
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.list_registers = clk_rcg2_list_registers,
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};
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EXPORT_SYMBOL_GPL(clk_pixel_ops);
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@ -864,6 +917,7 @@ const struct clk_ops clk_gfx3d_ops = {
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.set_rate = clk_gfx3d_set_rate,
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.set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
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.determine_rate = clk_gfx3d_determine_rate,
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.list_registers = clk_rcg2_list_registers,
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};
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EXPORT_SYMBOL_GPL(clk_gfx3d_ops);
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@ -944,5 +998,7 @@ const struct clk_ops clk_gfx3d_src_ops = {
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.set_rate = clk_gfx3d_set_rate,
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.set_rate_and_parent = clk_gfx3d_src_set_rate_and_parent,
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.determine_rate = clk_gfx3d_src_determine_rate,
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.list_rate = clk_rcg2_list_rate,
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.list_registers = clk_rcg2_list_registers,
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};
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EXPORT_SYMBOL_GPL(clk_gfx3d_src_ops);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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* Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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@ -15,6 +15,7 @@
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#define __QCOM_CLK_REGMAP_H__
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#include <linux/clk-provider.h>
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#include <linux/debugfs.h>
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struct regmap;
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@ -42,4 +43,9 @@ void clk_disable_regmap(struct clk_hw *hw);
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struct clk *
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devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk);
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struct clk_register_data {
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char *name;
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u32 offset;
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};
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#endif
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