drm/msm: gpu: Add support for the GPMU
Most 5XX targets have GPMU (Graphics Power Management Unit) that handles a lot of the heavy lifting for power management including thermal and limits management and dynamic power collapse. While the GPMU itself is optional, it is usually nessesary to hit aggressive power targets. If the GPMU is to be used a filename and minimum version are defined in the device tree. The GPMU firmware needs to be loaded into the GPMU at init time via a shared hardware block of registers. Using the GPU to write the microcode is more efficient than using the CPU so at first load create an indirect buffer that can be executed during subsequent initalization sequences. After loading the GPMU gets initalized through a shared register interface and then we mostly get out of its way and let it do its thing. Change-Id: Ic0dedbad8d899177919b71500f2e944b187e87c0 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
This commit is contained in:
Jordan Crouse
parent
045b6f0aab
commit
0a7274232b
5 changed files with 576 additions and 2 deletions
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@ -53,7 +53,8 @@ msm_drm-y += adreno/adreno_device.o \
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adreno/adreno_gpu.o \
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adreno/a3xx_gpu.o \
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adreno/a4xx_gpu.o \
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adreno/a5xx_gpu.o
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adreno/a5xx_gpu.o \
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adreno/a5xx_power.o
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endif
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msm_drm-$(CONFIG_DRM_MSM_MDP4) += mdp/mdp4/mdp4_crtc.o \
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@ -463,6 +463,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
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gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
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/* Load the GPMU firmware before starting the HW init */
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a5xx_gpmu_ucode_init(gpu);
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ret = adreno_hw_init(gpu);
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if (ret)
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return ret;
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@ -480,6 +483,10 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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if (ret)
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return ret;
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ret = a5xx_power_init(gpu);
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if (ret)
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return ret;
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/*
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* Send a pipeline event stat to get misbehaving counters to start
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* ticking correctly
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@ -535,6 +542,12 @@ static void a5xx_destroy(struct msm_gpu *gpu)
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drm_gem_object_unreference_unlocked(a5xx_gpu->pfp_bo);
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}
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if (a5xx_gpu->gpmu_bo) {
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if (a5xx_gpu->gpmu_iova)
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msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->aspace);
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drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo);
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}
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adreno_gpu_cleanup(adreno_gpu);
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kfree(a5xx_gpu);
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}
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@ -777,11 +790,55 @@ static void a5xx_dump(struct msm_gpu *gpu)
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static int a5xx_pm_resume(struct msm_gpu *gpu)
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{
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return msm_gpu_pm_resume(gpu);
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int ret;
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/* Turn on the core power */
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ret = msm_gpu_pm_resume(gpu);
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if (ret)
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return ret;
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/* Turn the RBCCU domain first to limit the chances of voltage droop */
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gpu_write(gpu, REG_A5XX_GPMU_RBCCU_POWER_CNTL, 0x778000);
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/* Wait 3 usecs before polling */
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udelay(3);
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ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS,
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(1 << 20), (1 << 20));
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if (ret) {
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DRM_ERROR("%s: timeout waiting for RBCCU GDSC enable: %X\n",
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gpu->name,
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gpu_read(gpu, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS));
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return ret;
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}
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/* Turn on the SP domain */
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gpu_write(gpu, REG_A5XX_GPMU_SP_POWER_CNTL, 0x778000);
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ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_SP_PWR_CLK_STATUS,
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(1 << 20), (1 << 20));
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if (ret)
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DRM_ERROR("%s: timeout waiting for SP GDSC enable\n",
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gpu->name);
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return ret;
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}
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static int a5xx_pm_suspend(struct msm_gpu *gpu)
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{
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/* Clear the VBIF pipe before shutting down */
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gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0xF);
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spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) & 0xF) == 0xF);
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gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0);
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/*
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* Reset the VBIF before power collapse to avoid issue with FIFO
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* entries
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*/
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gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000);
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gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000);
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return msm_gpu_pm_suspend(gpu);
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}
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@ -826,6 +883,65 @@ static const struct adreno_gpu_funcs funcs = {
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.get_timestamp = a5xx_get_timestamp,
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};
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/* Read the limits management leakage from the efuses */
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static void a530_efuse_leakage(struct platform_device *pdev,
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struct adreno_gpu *adreno_gpu, void *base,
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size_t size)
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{
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struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
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unsigned int row0, row2;
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unsigned int leakage_pwr_on, coeff;
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if (size < 0x148)
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return;
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/* Leakage */
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row0 = readl_relaxed(base + 0x134);
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row2 = readl_relaxed(base + 0x144);
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/* Read barrier to get the previous two reads */
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rmb();
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/* Get the leakage coefficient from device tree */
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if (of_property_read_u32(pdev->dev.of_node,
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"qcom,base-leakage-coefficent", &coeff))
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return;
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leakage_pwr_on = ((row2 >> 2) & 0xFF) * (1 << (row0 >> 1) & 0x03);
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a5xx_gpu->lm_leakage = (leakage_pwr_on << 16) |
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((leakage_pwr_on * coeff) / 100);
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}
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/* Read target specific configuration from the efuses */
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static void a5xx_efuses_read(struct platform_device *pdev,
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struct adreno_gpu *adreno_gpu)
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{
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struct adreno_platform_config *config = pdev->dev.platform_data;
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const struct adreno_info *info = adreno_info(config->rev);
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struct resource *res;
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void *base;
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/*
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* The adreno_gpu->revn mechanism isn't set up yet so we need to check
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* it directly here
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*/
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if (info->revn != 530)
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return;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"qfprom_memory");
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if (!res)
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return;
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base = ioremap(res->start, resource_size(res));
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if (!base)
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return;
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a530_efuse_leakage(pdev, adreno_gpu, base, resource_size(res));
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iounmap(base);
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}
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struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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@ -851,6 +967,11 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
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adreno_gpu->registers = a5xx_registers;
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adreno_gpu->reg_offsets = a5xx_register_offsets;
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a5xx_gpu->lm_leakage = 0x4E001A;
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/* Check the efuses for some configuration */
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a5xx_efuses_read(pdev, adreno_gpu);
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ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs);
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if (ret) {
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a5xx_destroy(&(a5xx_gpu->base.base));
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@ -30,8 +30,31 @@ struct a5xx_gpu {
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struct drm_gem_object *pfp_bo;
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uint64_t pfp_iova;
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struct drm_gem_object *gpmu_bo;
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uint64_t gpmu_iova;
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uint32_t gpmu_dwords;
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uint32_t lm_leakage;
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};
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#define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base)
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int a5xx_power_init(struct msm_gpu *gpu);
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void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
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static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs,
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uint32_t reg, uint32_t mask, uint32_t value)
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{
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while (usecs--) {
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udelay(1);
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if ((gpu_read(gpu, reg) & mask) == value)
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return 0;
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cpu_relax();
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}
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return -ETIMEDOUT;
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}
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#endif /* __A5XX_GPU_H__ */
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426
drivers/gpu/drm/msm/adreno/a5xx_power.c
Normal file
426
drivers/gpu/drm/msm/adreno/a5xx_power.c
Normal file
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@ -0,0 +1,426 @@
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/* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/pm_opp.h>
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#include "a5xx_gpu.h"
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/*
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* The GPMU data block is a block of shared registers that can be used to
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* communicate back and forth. These "registers" are by convention with the GPMU
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* firwmare and not bound to any specific hardware design
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*/
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#define AGC_INIT_BASE REG_A5XX_GPMU_DATA_RAM_BASE
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#define AGC_INIT_MSG_MAGIC (AGC_INIT_BASE + 5)
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#define AGC_MSG_BASE (AGC_INIT_BASE + 7)
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#define AGC_MSG_STATE (AGC_MSG_BASE + 0)
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#define AGC_MSG_COMMAND (AGC_MSG_BASE + 1)
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#define AGC_MSG_PAYLOAD_SIZE (AGC_MSG_BASE + 3)
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#define AGC_MSG_PAYLOAD(_o) ((AGC_MSG_BASE + 5) + (_o))
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#define AGC_POWER_CONFIG_PRODUCTION_ID 1
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#define AGC_INIT_MSG_VALUE 0xBABEFACE
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static struct {
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uint32_t reg;
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uint32_t value;
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} a5xx_sequence_regs[] = {
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{ 0xB9A1, 0x00010303 },
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{ 0xB9A2, 0x13000000 },
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{ 0xB9A3, 0x00460020 },
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{ 0xB9A4, 0x10000000 },
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{ 0xB9A5, 0x040A1707 },
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{ 0xB9A6, 0x00010000 },
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{ 0xB9A7, 0x0E000904 },
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{ 0xB9A8, 0x10000000 },
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{ 0xB9A9, 0x01165000 },
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{ 0xB9AA, 0x000E0002 },
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{ 0xB9AB, 0x03884141 },
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{ 0xB9AC, 0x10000840 },
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{ 0xB9AD, 0x572A5000 },
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{ 0xB9AE, 0x00000003 },
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{ 0xB9AF, 0x00000000 },
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{ 0xB9B0, 0x10000000 },
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{ 0xB828, 0x6C204010 },
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{ 0xB829, 0x6C204011 },
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{ 0xB82A, 0x6C204012 },
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{ 0xB82B, 0x6C204013 },
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{ 0xB82C, 0x6C204014 },
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{ 0xB90F, 0x00000004 },
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{ 0xB910, 0x00000002 },
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{ 0xB911, 0x00000002 },
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{ 0xB912, 0x00000002 },
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{ 0xB913, 0x00000002 },
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{ 0xB92F, 0x00000004 },
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{ 0xB930, 0x00000005 },
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{ 0xB931, 0x00000005 },
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{ 0xB932, 0x00000005 },
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{ 0xB933, 0x00000005 },
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{ 0xB96F, 0x00000001 },
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{ 0xB970, 0x00000003 },
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{ 0xB94F, 0x00000004 },
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{ 0xB950, 0x0000000B },
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{ 0xB951, 0x0000000B },
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{ 0xB952, 0x0000000B },
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{ 0xB953, 0x0000000B },
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{ 0xB907, 0x00000019 },
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{ 0xB927, 0x00000019 },
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{ 0xB947, 0x00000019 },
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{ 0xB967, 0x00000019 },
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{ 0xB987, 0x00000019 },
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{ 0xB906, 0x00220001 },
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{ 0xB926, 0x00220001 },
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{ 0xB946, 0x00220001 },
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{ 0xB966, 0x00220001 },
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{ 0xB986, 0x00300000 },
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{ 0xAC40, 0x0340FF41 },
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{ 0xAC41, 0x03BEFED0 },
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{ 0xAC42, 0x00331FED },
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{ 0xAC43, 0x021FFDD3 },
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{ 0xAC44, 0x5555AAAA },
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{ 0xAC45, 0x5555AAAA },
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{ 0xB9BA, 0x00000008 },
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};
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/*
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* Get the actual voltage value for the operating point at the specified
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* frequency
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*/
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static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq)
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{
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struct drm_device *dev = gpu->dev;
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struct msm_drm_private *priv = dev->dev_private;
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struct platform_device *pdev = priv->gpu_pdev;
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struct dev_pm_opp *opp;
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opp = dev_pm_opp_find_freq_exact(&pdev->dev, freq, true);
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return (!IS_ERR(opp)) ? dev_pm_opp_get_voltage(opp) / 1000 : 0;
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}
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/* Setup thermal limit management */
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static void a5xx_lm_setup(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
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uint32_t tsens = 0;
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uint32_t lm_limit = 6000;
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uint32_t max_power = 0;
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unsigned int i;
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/* Write the block of sequence registers */
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for (i = 0; i < ARRAY_SIZE(a5xx_sequence_regs); i++)
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gpu_write(gpu, a5xx_sequence_regs[i].reg,
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a5xx_sequence_regs[i].value);
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of_property_read_u32(GPU_OF_NODE(gpu), "qcom,gpmu-tsens", &tsens);
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gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, tsens);
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gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01);
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gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01);
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/* Until we get clock scaling 0 is always the active power level */
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gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0);
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gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage);
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of_property_read_u32(GPU_OF_NODE(gpu), "qcom,lm-limit", &lm_limit);
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gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | lm_limit);
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gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF);
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gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x00201FF1);
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/* Write the voltage table */
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/* Get the max-power from the device tree */
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of_property_read_u32(GPU_OF_NODE(gpu), "qcom,lm-max-power", &max_power);
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gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF);
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gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x201FF1);
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gpu_write(gpu, AGC_MSG_STATE, 1);
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gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID);
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/*
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* For now just write the one voltage level - we will do more when we
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* can do scaling
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*/
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gpu_write(gpu, AGC_MSG_PAYLOAD(0), max_power);
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gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1);
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gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate));
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gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000);
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gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, 4 * sizeof(uint32_t));
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gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE);
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}
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/* Enable SP/TP cpower collapse */
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static void a5xx_pc_init(struct msm_gpu *gpu)
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{
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gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL, 0x7F);
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gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_BINNING_CTRL, 0);
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gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST, 0xA0080);
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gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY, 0x600040);
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}
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/* Enable the GPMU microcontroller */
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static int a5xx_gpmu_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
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struct msm_ringbuffer *ring = gpu->rb;
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if (!a5xx_gpu->gpmu_dwords)
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return 0;
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/* Turn off protected mode for this operation */
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OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
|
||||
OUT_RING(ring, 0);
|
||||
|
||||
/* Kick off the IB to load the GPMU microcode */
|
||||
OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
|
||||
OUT_RING(ring, lower_32_bits(a5xx_gpu->gpmu_iova));
|
||||
OUT_RING(ring, upper_32_bits(a5xx_gpu->gpmu_iova));
|
||||
OUT_RING(ring, a5xx_gpu->gpmu_dwords);
|
||||
|
||||
/* Turn back on protected mode */
|
||||
OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
|
||||
OUT_RING(ring, 1);
|
||||
|
||||
gpu->funcs->flush(gpu);
|
||||
|
||||
if (!gpu->funcs->idle(gpu)) {
|
||||
DRM_ERROR("%s: Unable to load GPMU firmware. GPMU will not be active\n",
|
||||
gpu->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
gpu_write(gpu, REG_A5XX_GPMU_WFI_CONFIG, 0x4014);
|
||||
|
||||
/* Kick off the GPMU */
|
||||
gpu_write(gpu, REG_A5XX_GPMU_CM3_SYSRESET, 0x0);
|
||||
|
||||
/*
|
||||
* Wait for the GPMU to respond. It isn't fatal if it doesn't, we just
|
||||
* won't have advanced power collapse.
|
||||
*/
|
||||
if (spin_usecs(gpu, 25, REG_A5XX_GPMU_GENERAL_0, 0xFFFFFFFF,
|
||||
0xBABEFACE))
|
||||
DRM_ERROR("%s: GPMU firmware initialization timed out\n",
|
||||
gpu->name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Enable limits management */
|
||||
static void a5xx_lm_enable(struct msm_gpu *gpu)
|
||||
{
|
||||
gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0);
|
||||
gpu_write(gpu, REG_A5XX_GDPM_INT_EN, 0x0A);
|
||||
gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK, 0x01);
|
||||
gpu_write(gpu, REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK, 0x50000);
|
||||
gpu_write(gpu, REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL, 0x30000);
|
||||
|
||||
gpu_write(gpu, REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL, 0x011);
|
||||
}
|
||||
|
||||
int a5xx_power_init(struct msm_gpu *gpu)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Set up the limits management */
|
||||
a5xx_lm_setup(gpu);
|
||||
|
||||
/* Set up SP/TP power collpase */
|
||||
a5xx_pc_init(gpu);
|
||||
|
||||
/* Start the GPMU */
|
||||
ret = a5xx_gpmu_init(gpu);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Start the limits management */
|
||||
a5xx_lm_enable(gpu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _read_header(unsigned int *data, uint32_t fwsize,
|
||||
unsigned int *major, unsigned int *minor)
|
||||
{
|
||||
uint32_t size;
|
||||
unsigned int i;
|
||||
|
||||
/* First dword of the header is the header size */
|
||||
if (fwsize < 4)
|
||||
return -EINVAL;
|
||||
|
||||
size = data[0];
|
||||
|
||||
/* Make sure the header isn't too big and is a multiple of two */
|
||||
if ((size % 2) || (size > 10) || size > (fwsize >> 2))
|
||||
return -EINVAL;
|
||||
|
||||
/* Read the values in pairs */
|
||||
for (i = 1; i < size; i += 2) {
|
||||
switch (data[i]) {
|
||||
case 1:
|
||||
*major = data[i + 1];
|
||||
break;
|
||||
case 2:
|
||||
*minor = data[i + 1];
|
||||
break;
|
||||
default:
|
||||
/* Invalid values are non fatal */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Make sure cur_major and cur_minor are greater than or equal to the minimum
|
||||
* allowable major/minor
|
||||
*/
|
||||
static inline bool _check_gpmu_version(uint32_t cur_major, uint32_t cur_minor,
|
||||
uint32_t min_major, uint32_t min_minor)
|
||||
{
|
||||
return ((cur_major > min_major) ||
|
||||
((cur_major == min_major) && (cur_minor >= min_minor)));
|
||||
}
|
||||
|
||||
void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
|
||||
struct drm_device *drm = gpu->dev;
|
||||
const char *name;
|
||||
const struct firmware *fw;
|
||||
uint32_t version[2] = { 0, 0 };
|
||||
uint32_t dwords = 0, offset = 0;
|
||||
uint32_t major = 0, minor = 0, bosize;
|
||||
unsigned int *data, *ptr, *cmds;
|
||||
unsigned int cmds_size;
|
||||
|
||||
if (a5xx_gpu->gpmu_bo)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Read the firmware name from the device tree - if it doesn't exist
|
||||
* then don't initialize the GPMU for this target
|
||||
*/
|
||||
if (of_property_read_string(GPU_OF_NODE(gpu), "qcom,gpmu-firmware",
|
||||
&name))
|
||||
return;
|
||||
|
||||
/*
|
||||
* The version isn't mandatory, but if it exists, we need to enforce
|
||||
* that the version of the GPMU firmware matches or is newer than the
|
||||
* value
|
||||
*/
|
||||
of_property_read_u32_array(GPU_OF_NODE(gpu), "qcom,gpmu-version",
|
||||
version, 2);
|
||||
|
||||
/* Get the firmware */
|
||||
if (request_firmware(&fw, name, drm->dev)) {
|
||||
DRM_ERROR("%s: Could not get GPMU firmware. GPMU will not be active\n",
|
||||
gpu->name);
|
||||
return;
|
||||
}
|
||||
|
||||
data = (unsigned int *) fw->data;
|
||||
|
||||
/*
|
||||
* The first dword is the size of the remaining data in dwords. Use it
|
||||
* as a checksum of sorts and make sure it matches the actual size of
|
||||
* the firmware that we read
|
||||
*/
|
||||
|
||||
if (fw->size < 8 || (data[0] < 2) || (data[0] >= (fw->size >> 2)))
|
||||
goto out;
|
||||
|
||||
/* The second dword is an ID - look for 2 (GPMU_FIRMWARE_ID) */
|
||||
if (data[1] != 2)
|
||||
goto out;
|
||||
|
||||
/* Read the header and get the major/minor of the read firmware */
|
||||
if (_read_header(&data[2], fw->size - 8, &major, &minor))
|
||||
goto out;
|
||||
|
||||
if (!_check_gpmu_version(major, minor, version[0], version[1])) {
|
||||
DRM_ERROR("%s: Loaded GPMU version %d.%d is too old\n",
|
||||
gpu->name, major, minor);
|
||||
goto out;
|
||||
}
|
||||
|
||||
cmds = data + data[2] + 3;
|
||||
cmds_size = data[0] - data[2] - 2;
|
||||
|
||||
/*
|
||||
* A single type4 opcode can only have so many values attached so
|
||||
* add enough opcodes to load the all the commands
|
||||
*/
|
||||
bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2;
|
||||
|
||||
mutex_lock(&drm->struct_mutex);
|
||||
a5xx_gpu->gpmu_bo = msm_gem_new(drm, bosize, MSM_BO_UNCACHED);
|
||||
mutex_unlock(&drm->struct_mutex);
|
||||
|
||||
if (IS_ERR(a5xx_gpu->gpmu_bo))
|
||||
goto err;
|
||||
|
||||
if (msm_gem_get_iova(a5xx_gpu->gpmu_bo, gpu->aspace,
|
||||
&a5xx_gpu->gpmu_iova))
|
||||
goto err;
|
||||
|
||||
ptr = msm_gem_vaddr(a5xx_gpu->gpmu_bo);
|
||||
if (!ptr)
|
||||
goto err;
|
||||
|
||||
while (cmds_size > 0) {
|
||||
int i;
|
||||
uint32_t _size = cmds_size > TYPE4_MAX_PAYLOAD ?
|
||||
TYPE4_MAX_PAYLOAD : cmds_size;
|
||||
|
||||
ptr[dwords++] = PKT4(REG_A5XX_GPMU_INST_RAM_BASE + offset,
|
||||
_size);
|
||||
|
||||
for (i = 0; i < _size; i++)
|
||||
ptr[dwords++] = *cmds++;
|
||||
|
||||
offset += _size;
|
||||
cmds_size -= _size;
|
||||
}
|
||||
|
||||
a5xx_gpu->gpmu_dwords = dwords;
|
||||
|
||||
goto out;
|
||||
|
||||
err:
|
||||
if (a5xx_gpu->gpmu_iova)
|
||||
msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->aspace);
|
||||
if (a5xx_gpu->gpmu_bo)
|
||||
drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo);
|
||||
|
||||
a5xx_gpu->gpmu_bo = NULL;
|
||||
a5xx_gpu->gpmu_iova = 0;
|
||||
a5xx_gpu->gpmu_dwords = 0;
|
||||
|
||||
out:
|
||||
/* No need to keep that firmware laying around anymore */
|
||||
release_firmware(fw);
|
||||
}
|
||||
|
|
@ -148,6 +148,9 @@ struct adreno_platform_config {
|
|||
__ret; \
|
||||
})
|
||||
|
||||
#define GPU_OF_NODE(_g) \
|
||||
(((struct msm_drm_private *) \
|
||||
((_g)->dev->dev_private))->gpu_pdev->dev.of_node)
|
||||
|
||||
static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue