evie/android_kernel_oneplus_msm8998
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ARM: dts: msm: update CPU efficiency property

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Update CPU efficiency property for msmcobalt so that scheduler can utilize
for task placement decision.

CRs-fixed: 1006303
Change-Id: Ifb59d6b1fcb1207053438786df2472417a2db93f
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
This commit is contained in:
Joonwoo Park 2016-03-21 11:34:11 -07:00 • committed by Jeevan Shriram
parent 16c433e4c5
commit 0af7da0589
1 changed files with 8 additions and 0 deletions
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8
arch/arm/boot/dts/qcom/msmcobalt.dtsi
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@ -45,6 +45,7 @@
reg = <0x0 0x0>;
qcom,limits-info = <&mitigation_profile0>;
enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>;
qcom,ea = <&ea0>;
L2_0: l2-cache {
@ -68,6 +69,7 @@
reg = <0x0 0x1>;
qcom,limits-info = <&mitigation_profile1>;
enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>;
qcom,ea = <&ea1>;
L1_I_1: l1-icache {
@ -86,6 +88,7 @@
reg = <0x0 0x2>;
qcom,limits-info = <&mitigation_profile2>;
enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>;
qcom,ea = <&ea2>;
L1_I_2: l1-icache {
@ -104,6 +107,7 @@
reg = <0x0 0x3>;
qcom,limits-info = <&mitigation_profile3>;
enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>;
qcom,ea = <&ea3>;
L1_I_3: l1-icache {
@ -122,6 +126,7 @@
reg = <0x0 0x100>;
qcom,limits-info = <&mitigation_profile4>;
enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>;
qcom,ea = <&ea4>;
L2_1: l2-cache {
@ -144,6 +149,7 @@
reg = <0x0 0x101>;
qcom,limits-info = <&mitigation_profile5>;
enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>;
qcom,ea = <&ea5>;
L1_I_101: l1-icache {
@ -162,6 +168,7 @@
reg = <0x0 0x102>;
qcom,limits-info = <&mitigation_profile6>;
enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>;
qcom,ea = <&ea6>;
L1_I_102: l1-icache {
@ -180,6 +187,7 @@
reg = <0x0 0x103>;
qcom,limits-info = <&mitigation_profile7>;
enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>;
qcom,ea = <&ea7>;
L1_I_103: l1-icache {