clk: qcom: Update the dp pixel clock flags

Display port pixel clock source is required to propagate the set rate to
parent, so update the flags for the same. The lowsvs frequency has got
updated to 154MHz, update the same.

Change-Id: I67a5ff3b5fb18c2ce986c5f431f4e41a78fe13a5
Signed-off-by: Taniya Das <tdas@codeaurora.org>

drivers/clk/qcom/mmcc-sdm660.c

@@ -965,8 +965,9 @@ static struct clk_rcg2 dp_pixel_clk_src = {
 		.parent_names = mmcc_parent_names_6,
 		.num_parents = 4,
 		.ops = &clk_dp_ops,
+		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 		VDD_DIG_FMAX_MAP3(
-			LOWER, 148380,
+			LOWER, 154000,
 			LOW, 296740,
 			NOMINAL, 593470),
 	},