Merge "ARM: dts: msm: Add support for GDSCs for MSMFalcon/MSMtriton"
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159
arch/arm/boot/dts/qcom/msm-gdsc-falcon.dtsi
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159
arch/arm/boot/dts/qcom/msm-gdsc-falcon.dtsi
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@ -0,0 +1,159 @@
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/*
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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/* GCC GDSCs */
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gdsc_usb30: qcom,gdsc@10f004 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_usb30";
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reg = <0x10f004 0x4>;
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status = "disabled";
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};
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gdsc_ufs: qcom,gdsc@175004 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_ufs";
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reg = <0x175004 0x4>;
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status = "disabled";
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};
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gdsc_hlos1_vote_lpass_adsp: qcom,gdsc@17d034 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_hlos1_vote_lpass_adsp";
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reg = <0x17d034 0x4>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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gdsc_hlos1_vote_turing_adsp: qcom,gdsc@17d04c {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_hlos1_vote_turing_adsp";
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reg = <0x17d04c 0x4>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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gdsc_hlos2_vote_turing_adsp: qcom,gdsc@17e04c {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_hlos2_vote_turing_adsp";
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reg = <0x17e04c 0x4>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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/* MMSS GDSCs */
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bimc_smmu_hw_ctrl: syscon@c8ce024 {
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compatible = "syscon";
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reg = <0xc8ce024 0x4>;
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};
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gdsc_bimc_smmu: qcom,gdsc@c8ce020 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_bimc_smmu";
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reg = <0xc8ce020 0x4>;
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hw-ctrl-addr = <&bimc_smmu_hw_ctrl>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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gdsc_venus: qcom,gdsc@c8c1024 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_venus";
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reg = <0xc8c1024 0x4>;
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status = "disabled";
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};
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gdsc_venus_core0: qcom,gdsc@c8c1040 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_venus_core0";
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reg = <0xc8c1040 0x4>;
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status = "disabled";
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};
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gdsc_camss_top: qcom,gdsc@c8c34a0 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_camss_top";
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reg = <0xc8c34a0 0x4>;
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status = "disabled";
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};
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gdsc_vfe0: qcom,gdsc@c8c3664 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_vfe0";
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reg = <0xc8c3664 0x4>;
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status = "disabled";
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};
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gdsc_vfe1: qcom,gdsc@c8c3674 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_vfe1";
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reg = <0xc8c3674 0x4>;
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status = "disabled";
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};
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gdsc_cpp: qcom,gdsc@c8c36d4 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_cpp";
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reg = <0xc8c36d4 0x4>;
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status = "disabled";
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};
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gdsc_mdss: qcom,gdsc@c8c2304 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_mdss";
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reg = <0xc8c2304 0x4>;
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status = "disabled";
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};
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/* GPU GDSCs */
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gpu_cx_hw_ctrl: syscon@5066008 {
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compatible = "syscon";
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reg = <0x5066008 0x4>;
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};
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gdsc_gpu_cx: qcom,gdsc@5066004 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_gpu_cx";
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reg = <0x5066004 0x4>;
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hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <2000>;
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status = "disabled";
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};
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/* GPU GX GDSCs */
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gpu_gx_domain_addr: syscon@5065130 {
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compatible = "syscon";
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reg = <0x5065130 0x4>;
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};
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gpu_gx_sw_reset: syscon@5066090 {
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compatible = "syscon";
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reg = <0x5066090 0x4>;
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};
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gdsc_gpu_gx: qcom,gdsc@5066094 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_gpu_gx";
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reg = <0x5066094 0x4>;
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domain-addr = <&gpu_gx_domain_addr>;
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sw-reset = <&gpu_gx_sw_reset>;
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qcom,retain-periph;
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qcom,reset-aon-logic;
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status = "disabled";
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};
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};
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@ -675,7 +675,7 @@
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#include "msmfalcon-ion.dtsi"
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#include "msmfalcon-bus.dtsi"
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#include "msmfalcon-regulator.dtsi"
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#include "msm-gdsc-cobalt.dtsi"
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#include "msm-gdsc-falcon.dtsi"
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&gdsc_usb30 {
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clock-names = "core_clk";
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@ -699,6 +699,14 @@
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status = "ok";
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};
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&gdsc_hlos1_vote_turing_adsp {
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status = "ok";
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};
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&gdsc_hlos2_vote_turing_adsp {
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status = "ok";
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};
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&gdsc_venus {
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status = "ok";
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};
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@ -749,5 +757,6 @@
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&gdsc_gpu_cx {
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status = "ok";
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};
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#include "msm-pmfalcon.dtsi"
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#include "msm-pm2falcon.dtsi"
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@ -16,6 +16,7 @@
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#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
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/ {
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model = "Qualcomm Technologies, Inc. MSMTRITON";
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@ -543,3 +544,78 @@
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};
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#include "msmtriton-ion.dtsi"
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#include "msmfalcon-regulator.dtsi"
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#include "msm-gdsc-falcon.dtsi"
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&gdsc_usb30 {
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clock-names = "core_clk";
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clocks = <&clock_gcc GCC_USB30_MASTER_CLK>;
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status = "ok";
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};
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&gdsc_ufs {
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status = "ok";
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};
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&gdsc_bimc_smmu {
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clock-names = "bus_clk";
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clocks = <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
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proxy-supply = <&gdsc_bimc_smmu>;
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qcom,proxy-consumer-enable;
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status = "ok";
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};
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&gdsc_hlos1_vote_lpass_adsp {
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status = "ok";
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};
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&gdsc_venus {
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status = "ok";
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};
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&gdsc_venus_core0 {
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qcom,support-hw-trigger;
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status = "ok";
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};
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&gdsc_camss_top {
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status = "ok";
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};
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&gdsc_vfe0 {
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parent-supply = <&gdsc_camss_top>;
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status = "ok";
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};
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&gdsc_vfe1 {
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parent-supply = <&gdsc_camss_top>;
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status = "ok";
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};
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&gdsc_cpp {
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parent-supply = <&gdsc_camss_top>;
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status = "ok";
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};
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&gdsc_mdss {
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clock-names = "bus_clk", "rot_clk";
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clocks = <&clock_mmss MMSS_MDSS_AXI_CLK>,
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<&clock_mmss MMSS_MDSS_ROT_CLK>;
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proxy-supply = <&gdsc_mdss>;
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qcom,proxy-consumer-enable;
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status = "ok";
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};
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&gdsc_gpu_gx {
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clock-names = "bimc_core_clk", "core_clk", "core_root_clk";
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clocks = <&clock_gcc GCC_GPU_BIMC_GFX_CLK>,
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<&clock_gfx GPUCC_GFX3D_CLK>,
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<&clock_gfx GFX3D_CLK_SRC>;
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qcom,force-enable-root-clk;
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parent-supply = <&gfx_vreg_corner>;
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status = "ok";
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};
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&gdsc_gpu_cx {
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status = "ok";
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};
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