iommu: io-pgtable-arm: Use correct bitmask for pgd entry
Ensure that the bits larger than cfg->ias are masked out before mapping an address in a pagetable. This is required in order to map a sign-extended address into TTBR1; for other use cases the bits above cfg->ias are expected to be zero. Change-Id: I2463cef7e0238cf887dcc682977375eb08d6973b Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
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1 changed files with 6 additions and 1 deletions
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@ -69,9 +69,12 @@
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#define ARM_LPAE_PGD_IDX(l,d) \
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((l) == ARM_LPAE_START_LVL(d) ? ilog2(ARM_LPAE_PAGES_PER_PGD(d)) : 0)
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#define ARM_LPAE_LVL_MASK(l, d) \
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((l) == ARM_LPAE_START_LVL(d) ? (1 << (d)->pgd_bits) - 1 : \
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(1 << (d)->bits_per_level) - 1)
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#define ARM_LPAE_LVL_IDX(a,l,d) \
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(((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \
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((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
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ARM_LPAE_LVL_MASK(l, d))
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/* Calculate the block/page mapping size at level l for pagetable in d. */
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#define ARM_LPAE_BLOCK_SIZE(l,d) \
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@ -197,6 +200,7 @@ struct arm_lpae_io_pgtable {
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struct io_pgtable iop;
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int levels;
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unsigned int pgd_bits;
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size_t pgd_size;
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unsigned long pg_shift;
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unsigned long bits_per_level;
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@ -913,6 +917,7 @@ arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
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/* Calculate the actual size of our pgd (without concatenation) */
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pgd_bits = va_bits - (data->bits_per_level * (data->levels - 1));
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data->pgd_bits = pgd_bits;
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data->pgd_size = 1UL << (pgd_bits + ilog2(sizeof(arm_lpae_iopte)));
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data->iop.ops = (struct io_pgtable_ops) {
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