From 0d82ce80de3888da7d39253fa775b7991836e58a Mon Sep 17 00:00:00 2001 From: Ingrid Gallardo Date: Fri, 20 Feb 2015 11:18:33 -0800 Subject: [PATCH] msm: mdss: add support to configure per pipe qos lut This change adds support to set the qos lut for each real time and non real time rotator read clients. Qos lut is configurable through dtsi, so it can be adjusted per chipset. Change-Id: I423265032c4a618039cdcfdad0a1f963f45ae5c6 Signed-off-by: Ingrid Gallardo --- .../devicetree/bindings/fb/mdss-mdp.txt | 2 ++ drivers/video/fbdev/msm/mdss.h | 1 + drivers/video/fbdev/msm/mdss_mdp.c | 4 +++ drivers/video/fbdev/msm/mdss_mdp_hwio.h | 1 + drivers/video/fbdev/msm/mdss_mdp_pipe.c | 29 +++++++++++++++++++ 5 files changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/fb/mdss-mdp.txt b/Documentation/devicetree/bindings/fb/mdss-mdp.txt index 009c6a6ea2bb..94635f2d0109 100644 --- a/Documentation/devicetree/bindings/fb/mdss-mdp.txt +++ b/Documentation/devicetree/bindings/fb/mdss-mdp.txt @@ -340,6 +340,8 @@ Optional properties: depending upon system state. - qcom,mdss-default-ot-limit: This integer value indicates the default number of pending reads that can be allowed for the real time clients. +- qcom,mdss-default-pipe-qos-lut: This value is used to program the default qos lut + register for the rt clients and nrt rotator read clients. - qcom,mdss-clk-levels: This array indicates the mdp core clock level selection array. Core clock is calculated for each frame and hence depending upon calculated value, clock rate diff --git a/drivers/video/fbdev/msm/mdss.h b/drivers/video/fbdev/msm/mdss.h index 1a0388fef7a2..cf81137c9918 100644 --- a/drivers/video/fbdev/msm/mdss.h +++ b/drivers/video/fbdev/msm/mdss.h @@ -236,6 +236,7 @@ struct mdss_data_type { u32 rotator_ot_limit; u32 default_ot_limit; + u32 default_pipe_qos_lut; u32 mdp_irq_mask; u32 mdp_hist_irq_mask; diff --git a/drivers/video/fbdev/msm/mdss_mdp.c b/drivers/video/fbdev/msm/mdss_mdp.c index f21a7daf0d93..2f9d3c547098 100644 --- a/drivers/video/fbdev/msm/mdss_mdp.c +++ b/drivers/video/fbdev/msm/mdss_mdp.c @@ -2666,6 +2666,10 @@ static int mdss_mdp_parse_dt_misc(struct platform_device *pdev) "qcom,mdss-default-ot-limit", &data); mdata->default_ot_limit = (!rc ? data : 0); + rc = of_property_read_u32(pdev->dev.of_node, + "qcom,mdss-default-pipe-qos-lut", &data); + mdata->default_pipe_qos_lut = (!rc ? data : 0); + mdata->has_non_scalar_rgb = of_property_read_bool(pdev->dev.of_node, "qcom,mdss-has-non-scalar-rgb"); mdata->has_bwc = of_property_read_bool(pdev->dev.of_node, diff --git a/drivers/video/fbdev/msm/mdss_mdp_hwio.h b/drivers/video/fbdev/msm/mdss_mdp_hwio.h index 39dff7798a80..584748e0859e 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_hwio.h +++ b/drivers/video/fbdev/msm/mdss_mdp_hwio.h @@ -200,6 +200,7 @@ enum mdss_mdp_sspp_chroma_samp_type { #define MDSS_MDP_REG_SSPP_REQPRIO_FIFO_WM_0 0x050 #define MDSS_MDP_REG_SSPP_REQPRIO_FIFO_WM_1 0x054 #define MDSS_MDP_REG_SSPP_REQPRIO_FIFO_WM_2 0x058 +#define MDSS_MDP_REG_SSPP_CREQ_LUT 0x068 #define MDSS_MDP_REG_SSPP_QOS_CTRL 0x06C #define MDSS_MDP_REG_SSPP_UBWC_ERROR_STATUS 0x138 diff --git a/drivers/video/fbdev/msm/mdss_mdp_pipe.c b/drivers/video/fbdev/msm/mdss_mdp_pipe.c index 4539c6f065ca..f909c0f22125 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_pipe.c +++ b/drivers/video/fbdev/msm/mdss_mdp_pipe.c @@ -56,6 +56,33 @@ static inline u32 mdss_mdp_pipe_read(struct mdss_mdp_pipe *pipe, u32 reg) return readl_relaxed(pipe->base + reg); } +int mdss_mdp_pipe_qos_lut(struct mdss_mdp_pipe *pipe) +{ + struct mdss_data_type *mdata = mdss_mdp_get_mdata(); + struct mdss_mdp_ctl *ctl = pipe->mixer_left->ctl; + u32 qos_lut = mdata->default_pipe_qos_lut; + + if (!qos_lut) + goto end; + + /* set lowest priority lut for non-real time wfd */ + if ((ctl->intf_num == MDSS_MDP_NO_INTF) && + !pipe->mixer_left->rotator_mode) + qos_lut = 0; + + pr_debug("lut:0x%x wfd:%d\n", qos_lut, + ((ctl->intf_num == MDSS_MDP_NO_INTF) && + !pipe->mixer_left->rotator_mode)); + + mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON); + mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_SSPP_CREQ_LUT, + qos_lut); + mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF); + +end: + return 0; +} + int mdss_mdp_pipe_panic_signal_ctrl(struct mdss_mdp_pipe *pipe, bool enable) { uint32_t panic_robust_ctrl; @@ -1825,6 +1852,8 @@ int mdss_mdp_pipe_queue_data(struct mdss_mdp_pipe *pipe, mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_VIG_OP_MODE, opmode); + mdss_mdp_pipe_qos_lut(pipe); + mdss_mdp_pipe_panic_signal_ctrl(pipe, true); mdss_mdp_set_ot_limit_pipe(pipe);