evie/android_kernel_oneplus_msm8998
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msm: mdss: update the recovery sequence for DSI LP_RX_TIMEOUT/BTA_TIMEOUT

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The MDP timing generator line count check for DSI error recovery
from LP_RX_TIMEOUT/BTA_TIMEOUT needs to be performed after clearing
the FORCE_TX_STOP bits for DSI data/clock lanes and before enabling
back the DSI video mode engine. Update this sequence to recover the
MDP timing generator from halt state due to back pressure before
the check for line count.

Change-Id: I17ca4ed74e3e11f4e81108a33271f113117ab669
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
This commit is contained in:
Padmanabhan Komanduru 2017-03-28 18:50:29 +05:30
parent fec225ae45
commit 0f766ccdad
1 changed files with 24 additions and 18 deletions
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42
drivers/video/fbdev/msm/mdss_dsi_host.c
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@ -778,6 +778,12 @@ static void mdss_dsi_ctl_phy_reset(struct mdss_dsi_ctrl_pdata *ctrl, u32 event)
u32 loop = 10, u_dly = 200;
pr_debug("%s: MDSS DSI CTRL and PHY reset. ctrl-num = %d\n",
__func__, ctrl->ndx);
if (ctrl->panel_mode == DSI_CMD_MODE) {
pr_warn("ctl_phy_reset not applicable for cmd mode\n");
return;
}
if (event == DSI_EV_DLNx_FIFO_OVERFLOW) {
mask = BIT(20); /* clock lane only for overflow recovery */
} else if (event == DSI_EV_LP_RX_TIMEOUT) {
@ -792,15 +798,6 @@ static void mdss_dsi_ctl_phy_reset(struct mdss_dsi_ctrl_pdata *ctrl, u32 event)
ctrl0 = mdss_dsi_get_ctrl_by_index(DSI_CTRL_0);
ctrl1 = mdss_dsi_get_ctrl_by_index(DSI_CTRL_1);
if (ctrl0->recovery) {
rc = ctrl0->recovery->fxn(ctrl0->recovery->data,
MDP_INTF_DSI_VIDEO_FIFO_OVERFLOW);
if (rc < 0) {
pr_debug("%s: Target is in suspend/shutdown\n",
__func__);
return;
}
}
/*
* Disable PHY contention detection and receive.
* Configure the strength ctrl 1 register.
@ -874,6 +871,15 @@ static void mdss_dsi_ctl_phy_reset(struct mdss_dsi_ctrl_pdata *ctrl, u32 event)
MIPI_OUTP(ctrl0->ctrl_base + 0x0ac, ln_ctrl0 & ~mask);
MIPI_OUTP(ctrl1->ctrl_base + 0x0ac, ln_ctrl1 & ~mask);
if (ctrl0->recovery) {
rc = ctrl0->recovery->fxn(ctrl0->recovery->data,
MDP_INTF_DSI_VIDEO_FIFO_OVERFLOW);
if (rc < 0) {
pr_debug("%s: Target is in suspend/shutdown\n",
__func__);
return;
}
}
/* Enable Video mode for DSI controller */
MIPI_OUTP(ctrl0->ctrl_base + 0x004, data0);
MIPI_OUTP(ctrl1->ctrl_base + 0x004, data1);
@ -890,15 +896,6 @@ static void mdss_dsi_ctl_phy_reset(struct mdss_dsi_ctrl_pdata *ctrl, u32 event)
*/
udelay(200);
} else {
if (ctrl->recovery) {
rc = ctrl->recovery->fxn(ctrl->recovery->data,
MDP_INTF_DSI_VIDEO_FIFO_OVERFLOW);
if (rc < 0) {
pr_debug("%s: Target is in suspend/shutdown\n",
__func__);
return;
}
}
/* Disable PHY contention detection and receive */
MIPI_OUTP((ctrl->phy_io.base) + 0x0188, 0);
@ -951,6 +948,15 @@ static void mdss_dsi_ctl_phy_reset(struct mdss_dsi_ctrl_pdata *ctrl, u32 event)
__func__, ln0);
MIPI_OUTP(ctrl->ctrl_base + 0x0ac, ln_ctrl0 & ~mask);
if (ctrl->recovery) {
rc = ctrl->recovery->fxn(ctrl->recovery->data,
MDP_INTF_DSI_VIDEO_FIFO_OVERFLOW);
if (rc < 0) {
pr_debug("%s: Target is in suspend/shutdown\n",
__func__);
return;
}
}
/* Enable Video mode for DSI controller */
MIPI_OUTP(ctrl->ctrl_base + 0x004, data0);
/* Enable PHY contention detection and receiver */