evie/android_kernel_oneplus_msm8998
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drm/sde: add panel count to support multiple bridge chips

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When multiple bridge chips are connected to same interface, the
drm mode in the mode_set has combined timing parameters. For
each individual bridge chip, those timing parameters need to
be divided by panel count.

CRs-Fixed: 1085590
Change-Id: I9af0fa99ab6bcf9e09f4f7b372d53e6f1638e6d0
Signed-off-by: Jin Li <jinl@codeaurora.org>
This commit is contained in:
Jin Li 2016-11-03 10:46:51 -04:00 • committed by Gerrit - the friendly Code Review server
parent 6a6b7144c8
commit 0fe164a0e3
3 changed files with 15 additions and 0 deletions
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12
drivers/gpu/drm/msm/dba_bridge.c
View file

@ -35,6 +35,7 @@
* @hdmi_mode: HDMI or DVI mode for the sink
* @num_of_input_lanes: Number of input lanes in case of DSI/LVDS
* @pluggable: If it's pluggable
* @panel_count: Number of panels attached to this display
*/
struct dba_bridge {
struct drm_bridge base;
@ -49,6 +50,7 @@ struct dba_bridge {
bool hdmi_mode;
u32 num_of_input_lanes;
bool pluggable;
u32 panel_count;
};
#define to_dba_bridge(x) container_of((x), struct dba_bridge, base)
@ -226,9 +228,18 @@ static void _dba_bridge_mode_set(struct drm_bridge *bridge,
if (!bridge || !mode || !adjusted_mode || !d_bridge) {
SDE_ERROR("Invalid params\n");
return;
} else if (!d_bridge->panel_count) {
SDE_ERROR("Panel count is 0\n");
return;
}
d_bridge->mode = *adjusted_mode;
/* Adjust mode according to number of panels */
d_bridge->mode.hdisplay /= d_bridge->panel_count;
d_bridge->mode.hsync_start /= d_bridge->panel_count;
d_bridge->mode.hsync_end /= d_bridge->panel_count;
d_bridge->mode.htotal /= d_bridge->panel_count;
d_bridge->mode.clock /= d_bridge->panel_count;
}
static bool _dba_bridge_mode_fixup(struct drm_bridge *bridge,
@ -294,6 +305,7 @@ struct drm_bridge *dba_bridge_init(struct drm_device *dev,
bridge->hdmi_mode = data->hdmi_mode;
bridge->num_of_input_lanes = data->num_of_input_lanes;
bridge->pluggable = data->pluggable;
bridge->panel_count = data->panel_count;
bridge->base.funcs = &_dba_bridge_ops;
bridge->base.encoder = encoder;

2
drivers/gpu/drm/msm/dba_bridge.h
View file

@ -32,6 +32,7 @@
* @num_of_input_lanes: Number of input lanes in case of DSI/LVDS
* @precede_bridge: Precede bridge chip
* @pluggable: If it's pluggable
* @panel_count: Number of panels attached to this display
*/
struct dba_bridge_init {
const char *client_name;
@ -42,6 +43,7 @@ struct dba_bridge_init {
u32 num_of_input_lanes;
struct drm_bridge *precede_bridge;
bool pluggable;
u32 panel_count;
};
/**

1
drivers/gpu/drm/msm/dsi-staging/dsi_display.c
View file

@ -2140,6 +2140,7 @@ int dsi_display_drm_bridge_init(struct dsi_display *display,
init_data.hdmi_mode = panel->dba_config.hdmi_mode;
init_data.num_of_input_lanes = num_of_lanes;
init_data.precede_bridge = precede_bridge;
init_data.panel_count = display->panel_count;
dba_bridge = dba_bridge_init(display->drm_dev, enc,
&init_data);
if (IS_ERR_OR_NULL(dba_bridge)) {