ARM: dts: msm: Add GPU properties for Cobalt
Add device specific GPU properties for Cobalt. Add GPU DCVS and bus DCVS plan CR-fixed: 973565 Change-Id: I6c51be7eeb50c41d4cfa9f9548ebd48888ee1ac5 Signed-off-by: Lokesh Batra <lbatra@codeaurora.org> Signed-off-by: George Shen <sqiao@codeaurora.org> Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
This commit is contained in:
Lokesh Batra
David Keitel
parent
e3020f3887
commit
10a10539d0
2 changed files with 214 additions and 0 deletions
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arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi
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arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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pil_gpu: qcom,kgsl-hyp {
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compatible = "qcom,pil-tz-generic";
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qcom,pas-id = <13>;
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qcom,firmware-name = "a530_zap";
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memory-region = <&peripheral_mem>;
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};
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msm_bus: qcom,kgsl-busmon{
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label = "kgsl-busmon";
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compatible = "qcom,kgsl-busmon";
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};
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gpubw: qcom,gpubw {
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compatible = "qcom,devbw";
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governor = "bw_vbif";
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qcom,src-dst-ports = <26 512>;
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/*
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* active-only flag is used while registering the bus
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* governor.It helps release the bus vote when the CPU
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* subsystem is inactiv3
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*/
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qcom,active-only;
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qcom,bw-tbl =
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< 0 /* off */ >,
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< 762 /* 100 MHz */ >,
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< 1144 /* 150 MHz */ >,
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< 1525 /* 200 MHz */ >,
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< 2288 /* 300 MHz */ >,
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< 3143 /* 412 MHz */ >,
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< 4173 /* 547 MHz */ >,
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< 5195 /* 681 MHz */ >,
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< 5859 /* 768 MHz */ >,
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< 7759 /* 1017 MHz */ >,
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< 9887 /* 1296 MHz */ >,
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< 11863 /* 1555 MHz */ >,
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< 13763 /* 1804 MHz */ >;
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};
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msm_gpu: qcom,kgsl-3d0@5000000 {
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label = "kgsl-3d0";
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compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
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status = "ok";
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reg = <0x5000000 0x40000>;
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reg-names = "kgsl_3d0_reg_memory";
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interrupts = <0 300 0>;
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interrupt-names = "kgsl_3d0_irq";
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qcom,id = <0>;
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qcom,chipid = <0x05040000>;
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qcom,gpu-efuse-leakage = <0x00070130 24>;
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qcom,base-leakage-coefficient = <34>;
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qcom,lm-limit = <6000>;
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qcom,initial-pwrlevel = <4>;
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qcom,idle-timeout = <8>; //<HZ/12>
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/*
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* Timeout to enter deeper power saving state
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* from NAP.
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*/
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qcom,deep-nap-timeout = <2>; //<HZ/50>
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qcom,strtstp-sleepwake;
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clocks = <&clock_gpu clk_gpucc_gfx3d_clk>,
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<&clock_gcc clk_gcc_gpu_cfg_ahb_clk>,
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<&clock_gpu clk_gpucc_rbbmtimer_clk>,
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<&clock_gcc clk_gcc_bimc_gfx_clk>,
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<&clock_gcc clk_gcc_gpu_bimc_gfx_clk>,
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<&clock_gpu clk_gpucc_gfx3d_isense_clk>,
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<&clock_gpu clk_gpucc_rbcpr_clk>;
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clock-names = "core_clk", "iface_clk", "rbbmtimer_clk",
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"mem_clk", "mem_iface_clk", "isense_clk", "rbcpr_clk";
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/* Bus Scale Settings */
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qcom,gpubw-dev = <&gpubw>;
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qcom,bus-control;
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qcom,msm-bus,name = "grp3d";
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qcom,msm-bus,num-cases = <13>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<26 512 0 0>,
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<26 512 0 800000>, // 1 bus=100
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<26 512 0 1200000>, // 2 bus=150
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<26 512 0 1600000>, // 3 bus=200
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<26 512 0 2400000>, // 4 bus=300
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<26 512 0 3296000>, // 5 bus=412
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<26 512 0 4376000>, // 6 bus=547
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<26 512 0 5448000>, // 7 bus=681
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<26 512 0 6144000>, // 8 bus=768
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<26 512 0 8136000>, // 9 bus=1017
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<26 512 0 10368000>, // 10 bus=1296
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<26 512 0 12440000>, // 11 bus=1555
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<26 512 0 14432000>; // 12 bus=1804
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/* GDSC regulator names */
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regulator-names = "vddcx", "vdd";
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/* GDSC oxili regulators */
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vddcx-supply = <&gdsc_gpu_cx>;
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vdd-supply = <&gdsc_gpu_gx>;
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/* Power levels */
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qcom,gpu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <700000000>;
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qcom,bus-freq = <12>;
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qcom,bus-min = <11>;
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qcom,bus-max = <12>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <560000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <12>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <460000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <11>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <360000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <6>;
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qcom,bus-max = <8>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <290000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <180000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <1>;
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qcom,bus-max = <4>;
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <27000000>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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};
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kgsl_msm_iommu: qcom,kgsl-iommu {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x05040000 0x10000>;
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qcom,protect = <0x40000 0x10000>;
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qcom,micro-mmu-control = <0x6000>;
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clocks =<&clock_gcc clk_gcc_gpu_cfg_ahb_clk>,
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<&clock_gcc clk_gcc_bimc_gfx_clk>,
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<&clock_gcc clk_gcc_gpu_bimc_gfx_clk>;
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clock-names = "iface_clk", "mem_clk", "mem_iface_clk";
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qcom,secure_align_mask = <0xfff>;
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qcom,retention;
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qcom,hyp_secure_alloc;
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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label = "gfx3d_user";
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iommus = <&kgsl_smmu 0>;
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qcom,gpu-offset = <0x48000>;
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};
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gfx3d_secure: gfx3d_secure {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 2>;
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};
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};
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};
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@ -1651,3 +1651,4 @@
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#include "msmcobalt-vidc.dtsi"
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#include "msmcobalt-coresight.dtsi"
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#include "msmcobalt-bus.dtsi"
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#include "msmcobalt-gpu.dtsi"
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