adv7481: Update adv7481 driver on MSM8996
Add support for adv7481 to use CCI i2c interface and to changes to make it upto date with the A family. CRs-Fixed: 998927 Change-Id: If1c9104e3e28a78a886ba184a302e8a4085c0bfd Signed-off-by: Shiju Mathew <shijum@codeaurora.org>
This commit is contained in:
Shiju Mathew
Jingtao Chen
parent
c5685ec0f3
commit
10ce2a7380
3 changed files with 1249 additions and 533 deletions
20
Documentation/devicetree/bindings/arm/msm/adv7481.txt
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20
Documentation/devicetree/bindings/arm/msm/adv7481.txt
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@ -0,0 +1,20 @@
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ADV7481 chip driver (VIDEO_ADV7481)
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VIDEO_ADV7481 is a kernel platform driver that is used for video decoder
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and dual mode HDMI/MHL receiver.
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The devicetree representation of the VIDEO_ADV7481 block should be:
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Required properties
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- compatible: "qcom,adv7481"
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- qcom,slave-addr: The i2c slave address of adv7481 driver.
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- qcom,cci-master: The i2c master id to be used for adv7481 driver.
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Example:
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qcom,adv7481@0 {
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compatible = "qcom,adv7481";
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qcom,cci-master = <0>;
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qcom,slave-addr = <0x70>;
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};
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File diff suppressed because it is too large
Load diff
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@ -1,4 +1,4 @@
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/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -19,6 +19,9 @@
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#define ADV_REG_GETFIELD(val, field) \
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(((val) & (field##_BMSK)) >> (field##_SHFT))
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#define ADV_REG_RSTFIELD(val, field) \
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((val) & ~((field##_BMSK) << (field##_SHFT)))
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/* IO Map Registers */
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#define IO_REG_MAIN_RST_ADDR 0xFF
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#define IO_REG_MAIN_RST_VALUE 0xFF
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@ -62,12 +65,22 @@
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#define IO_CTRL_CSI4_IN_SEL_SHFT 2
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#define IO_PAD_CTRLS_ADDR 0x0E
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#define IO_PAD_FILTER_CTRLS_ADDR 0x0F
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#define IO_REG_I2C_CFG_ADDR 0xF2
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#define IO_REG_I2C_AUTOINC_EN_REG_VALUE 0x01
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#define IO_CTRL_MASTER_PWDN_REG_VALUE 0x01
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/* Interrupts */
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#define IO_HDMI_LVL_INT_CLEAR_1_ADDR 0x69
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#define IO_HDMI_LVL_INT_MASKB_1_ADDR 0x6B
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#define IO_AVI_INFO_MB1_BMSK 0x0001
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#define IO_AVI_INFO_MB1_SHFT 0
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#define IO_HDMI_LVL_INT_CLEAR_2_ADDR 0x6E
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#define IO_HDMI_LVL_RAW_STATUS_3_ADDR 0x71
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#define IO_TMDSPLL_LCK_A_RAW_BMSK 0x0080
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#define IO_TMDSPLL_LCK_A_RAW_SHFT 7
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@ -78,10 +91,13 @@
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#define IO_DE_REGEN_LCK_RAW_BMSK 0x0001
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#define IO_DE_REGEN_LCK_RAW_SHFT 0
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/* Interrupts */
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#define IO_HDMI_LVL_INT_STATUS_3_ADDR 0x72
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#define IO_CABLE_DET_A_ST_BMSK 0x0040
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#define IO_CABLE_DET_A_ST_SHFT 6
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#define IO_V_LOCKED_ST_BMSK 0x0002
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#define IO_V_LOCKED_ST_SHFT 1
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#define IO_DE_REGEN_LCK_ST_BMSK 0x0001
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#define IO_DE_REGEN_LCK_ST_SHFT 0
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#define IO_HDMI_LVL_INT_CLEAR_3_ADDR 0x73
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#define IO_CABLE_DET_A_CLR_BMSK 0x0040
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@ -94,6 +110,33 @@
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#define IO_HDMI_LVL_INT_MASKB_3_ADDR 0x75
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#define IO_CABLE_DET_A_MB1_BMSK 0x0040
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#define IO_CABLE_DET_A_MB1_SHFT 6
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#define IO_V_LOCKED_MB1_BMSK 0x0002
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#define IO_V_LOCKED_MB1_SHFT 1
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#define IO_DE_REGEN_LCK_MB1_BMSK 0x0001
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#define IO_DE_REGEN_LCK_MB1_SHFT 0
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#define IO_HDMI_EDG_RAW_STATUS_1_ADDR 0x80
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#define IO_NEW_AVI_INFO_RAW_BMSK 0x0001
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#define IO_NEW_AVI_INFO_RAW_SHFT 0
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#define IO_HDMI_EDG_INT_STATUS_1_ADDR 0x81
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#define IO_NEW_AVI_INFO_ST_BMSK 0x0001
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#define IO_NEW_AVI_INFO_ST_SHFT 0
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#define IO_HDMI_EDG_INT_CLEAR_1_ADDR 0x82
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#define IO_NEW_AVI_INFO_CLR_BMSK 0x0001
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#define IO_NEW_AVI_INFO_CLR_SHFT 0
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#define IO_HDMI_EDG_INT2_MASKB_1_ADDR 0x83
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#define IO_NEW_AVI_INFO_MB2_BMSK 0x0001
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#define IO_NEW_AVI_INFO_MB2_SHFT 0
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#define IO_HDMI_EDG_INT_MASKB_1_ADDR 0x84
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#define IO_NEW_AVI_INFO_MB1_BMSK 0x0001
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#define IO_NEW_AVI_INFO_MB1_SHFT 0
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#define IO_HDMI_EDG_INT_CLEAR_2_ADDR 0x87
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#define IO_HDMI_EDG_INT_CLEAR_3_ADDR 0x8C
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#define IO_REG_PAD_CTRL_1_ADDR 0x1D
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#define IO_PDN_INT1_BMSK 0x0080
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@ -108,6 +151,16 @@
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#define IO_DRV_LLC_PAD_SHFT 2
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#define IO_REG_INT_RAW_STATUS_ADDR 0x3F
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#define IO_INT_CEC_ST_BMSK 0x0010
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#define IO_INT_CEC_ST_SHFT 4
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#define IO_INT_HDMI_ST_BMSK 0x0008
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#define IO_INT_HDMI_ST_SHFT 3
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#define IO_INTRQ3_RAW_BMSK 0x0004
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#define IO_INTRQ3_RAW_SHFT 2
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#define IO_INTRQ2_RAW_BMSK 0x0002
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#define IO_INTRQ2_RAW_SHFT 1
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#define IO_INTRQ1_RAW_BMSK 0x0001
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#define IO_INTRQ1_RAW_SHFT 0
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#define IO_REG_INT1_CONF_ADDR 0x40
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#define IO_INTRQ_DUR_SEL_BMSK 0x00C0
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@ -128,7 +181,29 @@
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#define IO_INTRQ2_OP_SEL_SHFT 0
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#define IO_REG_DATAPATH_RAW_STATUS_ADDR 0x43
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#define IO_CP_LOCK_CP_RAW_BMSK 0x0080
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#define IO_CP_LOCK_CP_RAW_SHFT 7
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#define IO_CP_UNLOCK_CP_RAW_BMSK 0x0040
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#define IO_CP_UNLOCK_CP_RAW_SHFT 6
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#define IO_VMUTE_REQUEST_HDMI_RAW_BMSK 0x0020
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#define IO_VMUTE_REQUEST_HDMI_RAW_SHFT 5
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#define IO_MPU_STIM_INTRQ_RAW_BMSK 0x0002
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#define IO_MPU_STIM_INTRQ_RAW_SHFT 1
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#define IO_INT_SD_RAW_BMSK 0x0001
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#define IO_INT_SD_RAW_SHFT 0
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#define IO_REG_DATAPATH_INT_STATUS_ADDR 0x44
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#define IO_CP_LOCK_CP_ST_BMSK 0x0080
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#define IO_CP_LOCK_CP_ST_SHFT 7
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#define IO_CP_UNLOCK_CP_ST_BMSK 0x0040
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#define IO_CP_UNLOCK_CP_ST_SHFT 6
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#define IO_VMUTE_REQUEST_HDMI_ST_BMSK 0x0020
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#define IO_VMUTE_REQUEST_HDMI_ST_SHFT 5
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#define IO_MPU_STIM_INTRQ_ST_BMSK 0x0002
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#define IO_MPU_STIM_INTRQ_ST_SHFT 1
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#define IO_INT_SD_ST_BMSK 0x0001
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#define IO_INT_SD_ST_SHFT 0
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#define IO_REG_DATAPATH_INT_CLEAR_ADDR 0x45
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#define IO_REG_DATAPATH_INT_MASKB_ADDR 0x47
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@ -143,6 +218,9 @@
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#define IO_INT_SD_MB1_BMSK 0x0001
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#define IO_INT_SD_MB1_SHFT 0
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#define IO_REG_CHIP_REV_ID_1_ADDR 0xDF
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#define IO_REG_CHIP_REV_ID_2_ADDR 0xE0
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/* Offsets */
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#define IO_REG_DPLL_ADDR 0xF3
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#define IO_REG_CP_ADDR 0xF4
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@ -264,6 +342,42 @@
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#define HDMI_EDID_A_ENABLE_BMSK 0x0001
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#define HDMI_EDID_A_ENABLE_SHFT 0
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/* CEC Map Registers */
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#define CEC_REG_LOG_ADDR_MASK_ADDR 0x27
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#define CEC_REG_LOG_ADDR_MASK2_BMSK 0x0040
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#define CEC_REG_LOG_ADDR_MASK2_SHFT 6
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#define CEC_REG_LOG_ADDR_MASK1_BMSK 0x0020
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#define CEC_REG_LOG_ADDR_MASK1_SHFT 5
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#define CEC_REG_LOG_ADDR_MASK0_BMSK 0x0010
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#define CEC_REG_LOG_ADDR_MASK0_SHFT 4
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#define CEC_REG_ERROR_REPORT_MODE_BMSK 0x0008
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#define CEC_REG_ERROR_REPORT_MODE_SHFT 3
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#define CEC_REG_ERROR_REPORT_DET_BMSK 0x0004
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#define CEC_REG_ERROR_REPORT_DET_SHFT 2
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#define CEC_REG_FORCE_NACK_BMSK 0x0002
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#define CEC_REG_FORCE_NACK_SHFT 1
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#define CEC_REG_FORCE_IGNORE_BMSK 0x0001
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#define CEC_REG_FORCE_IGNORE_SHFT 0
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#define CEC_REG_LOGICAL_ADDRESS0_1_ADDR 0x28
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#define CEC_REG_LOGICAL_ADDRESS1_BMSK 0x00F0
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#define CEC_REG_LOGICAL_ADDRESS1_SHFT 4
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#define CEC_REG_LOGICAL_ADDRESS0_BMSK 0x000F
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#define CEC_REG_LOGICAL_ADDRESS0_SHFT 0
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#define CEC_REG_LOGICAL_ADDRESS2_ADDR 0x29
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#define CEC_REG_LOGICAL_ADDRESS2_BMSK 0x000F
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#define CEC_REG_LOGICAL_ADDRESS2_SHFT 0
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#define CEC_REG_CEC_POWER_UP_ADDR 0x2A
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#define CEC_REG_CEC_POWER_UP_BMSK 0x0001
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#define CEC_REG_CEC_POWER_UP_SHFT 0
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#define CEC_REG_CLR_RX_RDY_SFT_RST_ADDR 0x2C
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#define CEC_REG_CEC_SOFT_RESET_BMSK 0x0001
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#define CEC_REG_CEC_SOFT_RESET_SHFT 0
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/* CP Map Registers */
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#define CP_REG_CONTRAST 0x3A
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#define CP_REG_SATURATION 0x3B
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