evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Merge "ARM: dts: msm: Update clock gfx node for MSMfalcon/Triton"

Browse source
This commit is contained in:
Linux Build Service Account 2016-11-24 06:13:28 -08:00 • committed by Gerrit - the friendly Code Review server
commit 11c49a900c
7 changed files with 47 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
arch/arm/boot/dts/qcom/msmfalcon-rumi.dts
View file

@ -102,3 +102,8 @@
&pmfalcon_fg {
status = "disabled";
};
&clock_gfx {
compatible = "qcom,dummycc";
clock-output-names = "gfx_clocks";
};

23
arch/arm/boot/dts/qcom/msmfalcon.dtsi
View file

@ -467,8 +467,21 @@
};
clock_gfx: clock-controller@5065000 {
compatible = "qcom,dummycc";
clock-output-names = "gfx_clocks";
compatible = "qcom,gpucc-msmfalcon";
reg = <0x5065000 0x10000>;
vdd_dig_gfx-supply = <&pm2falcon_s3_level>;
vdd_mx_gfx-supply = <&pm2falcon_s5_level>;
vdd_gfx-supply = <&gfx_vreg_corner>;
qcom,gfxfreq-corner =
< 0 0>,
< 160000000 1>, /* MinSVS */
< 266000000 2>, /* LowSVS */
< 370000000 3>, /* SVS */
< 465000000 4>, /* SVS_L1 */
< 588000000 5>, /* NOM */
< 647000000 6>, /* NOM_L1 */
< 700000000 7>, /* TURBO */
< 750000000 7>; /* TURBO */
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -985,10 +998,8 @@
};
&gdsc_gpu_gx {
clock-names = "bimc_core_clk", "core_clk", "core_root_clk";
clocks = <&clock_gcc GCC_GPU_BIMC_GFX_CLK>,
<&clock_gfx GPUCC_GFX3D_CLK>,
<&clock_gfx GFX3D_CLK_SRC>;
clock-names = "core_root_clk";
clocks = <&clock_gfx GFX3D_CLK_SRC>;
qcom,force-enable-root-clk;
parent-supply = <&gfx_vreg_corner>;
status = "ok";

5
arch/arm/boot/dts/qcom/msmtriton-rumi.dts
View file

@ -63,3 +63,8 @@
compatible = "qcom,dummycc";
clock-output-names = "gcc_clocks";
};
&clock_gfx {
compatible = "qcom,dummycc";
clock-output-names = "gfx_clocks";
};

23
arch/arm/boot/dts/qcom/msmtriton.dtsi
View file

@ -382,8 +382,21 @@
};
clock_gfx: clock-controller@5065000 {
compatible = "qcom,dummycc";
clock-output-names = "gfx_clocks";
compatible = "qcom,gpucc-msmfalcon";
reg = <0x5065000 0x10000>;
vdd_dig_gfx-supply = <&pm2falcon_s3_level>;
vdd_mx_gfx-supply = <&pm2falcon_s5_level>;
vdd_gfx-supply = <&gfx_vreg_corner>;
qcom,gfxfreq-corner =
< 0 0>,
< 160000000 1>, /* MinSVS */
< 266000000 2>, /* LowSVS */
< 370000000 3>, /* SVS */
< 465000000 4>, /* SVS_L1 */
< 588000000 5>, /* NOM */
< 647000000 6>, /* NOM_L1 */
< 700000000 7>, /* TURBO */
< 750000000 7>; /* TURBO */
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -794,10 +807,8 @@
};
&gdsc_gpu_gx {
clock-names = "bimc_core_clk", "core_clk", "core_root_clk";
clocks = <&clock_gcc GCC_GPU_BIMC_GFX_CLK>,
<&clock_gfx GPUCC_GFX3D_CLK>,
<&clock_gfx GFX3D_CLK_SRC>;
clock-names = "core_root_clk";
clocks = <&clock_gfx GFX3D_CLK_SRC>;
qcom,force-enable-root-clk;
parent-supply = <&gfx_vreg_corner>;
status = "ok";

2
arch/arm/configs/msmfalcon_defconfig
View file

@ -422,7 +422,7 @@ CONFIG_RMNET_IPA3=y
CONFIG_GPIO_USB_DETECT=y
CONFIG_USB_BAM=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_MSM_GCC_FALCON=y
CONFIG_MSM_GPUCC_FALCON=y
CONFIG_REMOTE_SPINLOCK_MSM=y
CONFIG_ARM_SMMU=y
CONFIG_IOMMU_DEBUG=y

2
arch/arm64/configs/msmfalcon-perf_defconfig
View file

@ -489,7 +489,7 @@ CONFIG_GPIO_USB_DETECT=y
CONFIG_SEEMP_CORE=y
CONFIG_USB_BAM=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_MSM_GCC_FALCON=y
CONFIG_MSM_GPUCC_FALCON=y
CONFIG_REMOTE_SPINLOCK_MSM=y
CONFIG_IOMMU_IO_PGTABLE_FAST=y
CONFIG_ARM_SMMU=y

2
arch/arm64/configs/msmfalcon_defconfig
View file

@ -498,7 +498,7 @@ CONFIG_GPIO_USB_DETECT=y
CONFIG_SEEMP_CORE=y
CONFIG_USB_BAM=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_MSM_GCC_FALCON=y
CONFIG_MSM_GPUCC_FALCON=y
CONFIG_REMOTE_SPINLOCK_MSM=y
CONFIG_IOMMU_IO_PGTABLE_FAST=y
CONFIG_IOMMU_IO_PGTABLE_FAST_SELFTEST=y