ARM: shmobile: use FSI driver's audio clock on ap4evb
Current FSI driver can control audio clock without platform call-back functions This patch removed board-specific call-back/settings Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms@verge.net.au>
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50ce2da348
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1 changed files with 1 additions and 138 deletions
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@ -658,133 +658,16 @@ static struct platform_device lcdc_device = {
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/* FSI */
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/* FSI */
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#define IRQ_FSI evt2irq(0x1840)
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#define IRQ_FSI evt2irq(0x1840)
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static int __fsi_set_rate(struct clk *clk, long rate, int enable)
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{
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int ret = 0;
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if (rate <= 0)
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return ret;
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if (enable) {
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ret = clk_set_rate(clk, rate);
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if (0 == ret)
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ret = clk_enable(clk);
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} else {
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clk_disable(clk);
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}
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return ret;
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}
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static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
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{
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return __fsi_set_rate(clk, clk_round_rate(clk, rate), enable);
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}
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static int fsi_ak4642_set_rate(struct device *dev, int rate, int enable)
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{
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struct clk *fsia_ick;
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struct clk *fsiack;
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int ret = -EIO;
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fsia_ick = clk_get(dev, "icka");
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if (IS_ERR(fsia_ick))
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return PTR_ERR(fsia_ick);
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/*
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* FSIACK is connected to AK4642,
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* and use external clock pin from it.
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* it is parent of fsia_ick now.
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*/
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fsiack = clk_get_parent(fsia_ick);
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if (!fsiack)
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goto fsia_ick_out;
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/*
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* we get 1/1 divided clock by setting same rate to fsiack and fsia_ick
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*
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** FIXME **
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* Because the freq_table of external clk (fsiack) are all 0,
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* the return value of clk_round_rate became 0.
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* So, it use __fsi_set_rate here.
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*/
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ret = __fsi_set_rate(fsiack, rate, enable);
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if (ret < 0)
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goto fsiack_out;
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ret = __fsi_set_round_rate(fsia_ick, rate, enable);
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if ((ret < 0) && enable)
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__fsi_set_round_rate(fsiack, rate, 0); /* disable FSI ACK */
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fsiack_out:
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clk_put(fsiack);
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fsia_ick_out:
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clk_put(fsia_ick);
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return 0;
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}
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static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
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{
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struct clk *fsib_clk;
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struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
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long fsib_rate = 0;
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long fdiv_rate = 0;
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int ackmd_bpfmd;
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int ret;
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switch (rate) {
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case 44100:
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fsib_rate = rate * 256;
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ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
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break;
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case 48000:
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fsib_rate = 85428000; /* around 48kHz x 256 x 7 */
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fdiv_rate = rate * 256;
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ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
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break;
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default:
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pr_err("unsupported rate in FSI2 port B\n");
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return -EINVAL;
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}
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/* FSI B setting */
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fsib_clk = clk_get(dev, "ickb");
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if (IS_ERR(fsib_clk))
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return -EIO;
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ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
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if (ret < 0)
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goto fsi_set_rate_end;
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/* FSI DIV setting */
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ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
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if (ret < 0) {
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/* disable FSI B */
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if (enable)
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__fsi_set_round_rate(fsib_clk, fsib_rate, 0);
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goto fsi_set_rate_end;
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}
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ret = ackmd_bpfmd;
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fsi_set_rate_end:
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clk_put(fsib_clk);
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return ret;
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}
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static struct sh_fsi_platform_info fsi_info = {
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static struct sh_fsi_platform_info fsi_info = {
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.port_a = {
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.port_a = {
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.flags = SH_FSI_BRS_INV,
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.flags = SH_FSI_BRS_INV,
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.set_rate = fsi_ak4642_set_rate,
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},
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},
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.port_b = {
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.port_b = {
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.flags = SH_FSI_BRS_INV |
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.flags = SH_FSI_BRS_INV |
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SH_FSI_BRM_INV |
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SH_FSI_BRM_INV |
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SH_FSI_LRS_INV |
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SH_FSI_LRS_INV |
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SH_FSI_CLK_CPG |
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SH_FSI_FMT_SPDIF,
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SH_FSI_FMT_SPDIF,
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.set_rate = fsi_hdmi_set_rate,
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},
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},
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};
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};
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@ -1144,25 +1027,6 @@ out:
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clk_put(hdmi_ick);
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clk_put(hdmi_ick);
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}
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}
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static void __init fsi_init_pm_clock(void)
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{
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struct clk *fsia_ick;
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int ret;
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fsia_ick = clk_get(&fsi_device.dev, "icka");
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if (IS_ERR(fsia_ick)) {
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ret = PTR_ERR(fsia_ick);
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pr_err("Cannot get FSI ICK: %d\n", ret);
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return;
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}
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ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk);
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if (ret < 0)
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pr_err("Cannot set FSI-A parent: %d\n", ret);
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clk_put(fsia_ick);
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}
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/* TouchScreen */
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/* TouchScreen */
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#ifdef CONFIG_AP4EVB_QHD
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#ifdef CONFIG_AP4EVB_QHD
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# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
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# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
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@ -1476,7 +1340,6 @@ static void __init ap4evb_init(void)
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ARRAY_SIZE(domain_devices));
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ARRAY_SIZE(domain_devices));
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hdmi_init_pm_clock();
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hdmi_init_pm_clock();
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fsi_init_pm_clock();
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sh7372_pm_init();
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sh7372_pm_init();
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pm_clk_add(&fsi_device.dev, "spu2");
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pm_clk_add(&fsi_device.dev, "spu2");
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pm_clk_add(&lcdc1_device.dev, "hdmi");
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pm_clk_add(&lcdc1_device.dev, "hdmi");
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