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ARM: dove: Restructure SoC device tree descriptor

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This patch adds proper ranges for all mapped addresses within
dove SoC and moves the interrupt controller node inside the simple-bus
node.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Sebastian Hesselbarth 2012-09-25 02:02:16 +02:00 • committed by Jason Cooper
parent 3fbcd3d0a0
commit 138ee96048
1 changed files with 18 additions and 12 deletions
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30
arch/arm/boot/dts/dove.dtsi
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@ -4,27 +4,33 @@
compatible = "marvell,dove"; compatible = "marvell,dove";
model = "Marvell Armada 88AP510 SoC"; model = "Marvell Armada 88AP510 SoC";
interrupt-parent = <&intc>; soc@f1000000 {
intc: interrupt-controller {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xf1020204 0x04>,
<0xf1020214 0x04>;
};
mbus@f1000000 {
compatible = "simple-bus"; compatible = "simple-bus";
ranges = <0 0xf1000000 0x4000000>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-parent = <&intc>;
ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
l2: l2-cache { l2: l2-cache {
compatible = "marvell,tauros2-cache"; compatible = "marvell,tauros2-cache";
marvell,tauros2-cache-features = <0>; marvell,tauros2-cache-features = <0>;
}; };
intc: interrupt-controller {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x20204 0x04>, <0x20214 0x04>;
};
uart0: serial@12000 { uart0: serial@12000 {
compatible = "ns16550a"; compatible = "ns16550a";
reg = <0x12000 0x100>; reg = <0x12000 0x100>;