ASoC: msm8x16: Initial change for internal codec support

- Add support for internal codec driver.
- Add regmap support for internal codec

The code is migrated from msm-3.18 kernel at the below
commit -

commit <bbf356f8bd26039cf3e0b447c064de6e2455b101>
<Merge "thermal: qpnp-temp-alarm: add support for
GEN2 PMIC peripherals>

CRs-Fixed: 1046168
Change-Id: Ib0cd2ed579bd370cc8979cafcc14acb083a408b6
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Signed-off-by: Asish Bhattacharya <asishb@codeaurora.org>

Documentation/devicetree/bindings/sound/qcom-audio-dev.txt

@@ -725,6 +725,11 @@ Optional Properties:
 
 Example:
 
+	msm_dig_codec: qcom,msm-int-codec {
+		compatible = "qcom,msm_int_core_codec";
+		qcom,dig-cdc-base-addr = <0xc0f0000>;
+	};
+
 	sound {
 		compatible = "qcom,msm8x16-audio-codec";
 		qcom,model = "msm8x16-snd-card";

Documentation/devicetree/bindings/sound/wcd_codec.txt

@@ -375,7 +375,9 @@ i2c@f9925000 {
 
 Tombak audio CODEC in SPMI mode
 
- - compatible = "qcom,msm8x16_wcd_codec";
+ - compatible = "qcom,msm-codec-core",
+ - compatible = "qcom,pmic-codec-digital"
+ - compatible = "qcom,pmic-codec-analog"
  - reg: represents the slave base address provided to the peripheral.
  - interrupt-parent : The parent interrupt controller.
  - interrupts: List of interrupts in given SPMI peripheral.
@@ -427,8 +429,19 @@ Optional properties:
 				core register writes.
 
 Example:
+
+msm_dig_codec: qcom,msm-int-codec {
+	compatible = "qcom,msm_int_core_codec";
+	qcom,dig-cdc-base-addr = <0xc0f0000>;
+};
+
+msm8x16_wcd_codec@f100 {
+	compatible = "qcom,msm_int_pmic_analog_codec";
+	reg = <0xf100 0x100>;
+};
+
 msm8x16_wcd_codec@f000{
-	compatible = "qcom,msm8x16_wcd_codec";
+	compatible = "qcom,msm_int_pmic_digital_codec";
 	reg = <0xf000 0x100>;
 	interrupt-parent = <&spmi_bus>;
 	interrupts = <0x1 0xf0 0x0>,

sound/soc/codecs/Kconfig

@@ -739,9 +739,6 @@ config SND_SOC_WSA881X_ANALOG
         tristate
 	select REGMAP_I2C
 
-config SND_SOC_MSM8X16_WCD
-	tristate
-
 config SND_SOC_WCD9XXX
 	tristate
 	default y if SND_SOC_WCD9320=y || SND_SOC_WCD9330=y || SND_SOC_WCD9335=y
@@ -984,4 +981,7 @@ config SND_SOC_MSM_HDMI_CODEC_RX
 	help
 	HDMI audio drivers should be built only if the platform
         supports hdmi panel.
+
+source "sound/soc/codecs/msm8x16/Kconfig"
+
 endmenu

sound/soc/codecs/Makefile

@@ -140,7 +140,6 @@ audio-ext-clock-objs := audio-ext-clk.o
 snd-soc-wcd-cpe-objs := wcd_cpe_services.o wcd_cpe_core.o
 snd-soc-wsa881x-objs := wsa881x.o wsa881x-tables.o wsa881x-regmap.o wsa881x-temp-sensor.o
 snd-soc-wcd-mbhc-objs := wcd-mbhc-v2.o
-snd-soc-msm8952-wcd-objs := msm8x16-wcd.o msm8x16-wcd-tables.o
 snd-soc-wsa881x-analog-objs := wsa881x-analog.o wsa881x-tables-analog.o
 snd-soc-wsa881x-analog-objs += wsa881x-regmap-analog.o wsa881x-irq.o
 snd-soc-wcd-dsp-utils-objs := wcd-dsp-utils.o
@@ -348,7 +347,6 @@ obj-$(CONFIG_SND_SOC_WCD934X)	+= wcd934x/
 obj-$(CONFIG_AUDIO_EXT_CLK)	+= audio-ext-clock.o
 obj-$(CONFIG_SND_SOC_WCD9XXX)   += snd-soc-wcd9xxx.o
 obj-$(CONFIG_SND_SOC_WCD9XXX_V2) += snd-soc-wcd9xxx-v2.o
-obj-$(CONFIG_SND_SOC_MSM8X16_WCD)	+= snd-soc-msm8952-wcd.o msm8916-wcd-irq.o
 obj-$(CONFIG_SND_SOC_WCD_CPE)   += snd-soc-wcd-cpe.o
 obj-$(CONFIG_SND_SOC_WCD_MBHC)  += snd-soc-wcd-mbhc.o
 obj-$(CONFIG_SND_SOC_WSA881X)	+= snd-soc-wsa881x.o
@@ -416,3 +414,4 @@ obj-$(CONFIG_SND_SOC_MSM_STUB)  += snd-soc-msm-stub.o
 # Amp
 obj-$(CONFIG_SND_SOC_MAX9877)	+= snd-soc-max9877.o
 obj-$(CONFIG_SND_SOC_TPA6130A2)	+= snd-soc-tpa6130a2.o
+obj-y += msm8x16/

sound/soc/codecs/msm8x16/Kconfig

@@ -0,0 +1,3 @@
+
+config SND_SOC_MSM8X16_WCD
+	tristate "MSM Internal PMIC based codec"

sound/soc/codecs/msm8x16/Makefile

@@ -0,0 +1,3 @@
+snd-soc-msm8952-wcd-objs := msm8x16-wcd.o msm8x16-wcd-tables.o msm89xx-regmap.o
+obj-$(CONFIG_SND_SOC_MSM8X16_WCD)      += snd-soc-msm8952-wcd.o msm8916-wcd-irq.o
+

sound/soc/codecs/msm8x16/msm8916-wcd-irq.c

@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -56,20 +56,20 @@ char *irq_names[MAX_NUM_IRQS] = {
 };
 
 int order[MAX_NUM_IRQS] = {
-	MSM8X16_WCD_IRQ_SPKR_CNP,
-	MSM8X16_WCD_IRQ_SPKR_CLIP,
-	MSM8X16_WCD_IRQ_SPKR_OCP,
-	MSM8X16_WCD_IRQ_MBHC_INSREM_DET1,
-	MSM8X16_WCD_IRQ_MBHC_RELEASE,
-	MSM8X16_WCD_IRQ_MBHC_PRESS,
-	MSM8X16_WCD_IRQ_MBHC_INSREM_DET,
-	MSM8X16_WCD_IRQ_MBHC_HS_DET,
-	MSM8X16_WCD_IRQ_EAR_OCP,
-	MSM8X16_WCD_IRQ_HPHR_OCP,
-	MSM8X16_WCD_IRQ_HPHL_OCP,
-	MSM8X16_WCD_IRQ_EAR_CNP,
-	MSM8X16_WCD_IRQ_HPHR_CNP,
-	MSM8X16_WCD_IRQ_HPHL_CNP,
+	MSM89XX_IRQ_SPKR_CNP,
+	MSM89XX_IRQ_SPKR_CLIP,
+	MSM89XX_IRQ_SPKR_OCP,
+	MSM89XX_IRQ_MBHC_INSREM_DET1,
+	MSM89XX_IRQ_MBHC_RELEASE,
+	MSM89XX_IRQ_MBHC_PRESS,
+	MSM89XX_IRQ_MBHC_INSREM_DET,
+	MSM89XX_IRQ_MBHC_HS_DET,
+	MSM89XX_IRQ_EAR_OCP,
+	MSM89XX_IRQ_HPHR_OCP,
+	MSM89XX_IRQ_HPHL_OCP,
+	MSM89XX_IRQ_EAR_CNP,
+	MSM89XX_IRQ_HPHR_CNP,
+	MSM89XX_IRQ_HPHL_CNP,
 };
 
 enum wcd9xxx_spmi_pm_state {
@@ -101,18 +101,18 @@ void wcd9xxx_spmi_enable_irq(int irq)
 	pr_debug("%s: irqno =%d\n", __func__, irq);
 	if ((irq >= 0) && (irq <= 7)) {
 		snd_soc_update_bits(map.codec,
-				MSM8X16_WCD_A_DIGITAL_INT_EN_CLR,
+				MSM89XX_PMIC_DIGITAL_INT_EN_CLR,
 				(0x01 << irq), 0x00);
 		snd_soc_update_bits(map.codec,
-				MSM8X16_WCD_A_DIGITAL_INT_EN_SET,
+				MSM89XX_PMIC_DIGITAL_INT_EN_SET,
 				(0x01 << irq), (0x01 << irq));
 	}
 	if ((irq > 7) && (irq <= 15)) {
 		snd_soc_update_bits(map.codec,
-				MSM8X16_WCD_A_ANALOG_INT_EN_CLR,
+				MSM89XX_PMIC_ANALOG_INT_EN_CLR,
 				(0x01 << (irq - 8)), 0x00);
 		snd_soc_update_bits(map.codec,
-				MSM8X16_WCD_A_ANALOG_INT_EN_SET,
+				MSM89XX_PMIC_ANALOG_INT_EN_SET,
 				(0x01 << (irq - 8)), (0x01 << (irq - 8)));
 	}
 
@@ -130,19 +130,19 @@ void wcd9xxx_spmi_disable_irq(int irq)
 	pr_debug("%s: irqno =%d\n", __func__, irq);
 	if ((irq >= 0) && (irq <= 7)) {
 		snd_soc_update_bits(map.codec,
-				MSM8X16_WCD_A_DIGITAL_INT_EN_SET,
+				MSM89XX_PMIC_DIGITAL_INT_EN_SET,
 				(0x01 << (irq)), 0x00);
 		snd_soc_update_bits(map.codec,
-				MSM8X16_WCD_A_DIGITAL_INT_EN_CLR,
+				MSM89XX_PMIC_DIGITAL_INT_EN_CLR,
 				(0x01 << irq), (0x01 << irq));
 	}
 
 	if ((irq > 7) && (irq <= 15)) {
 		snd_soc_update_bits(map.codec,
-				MSM8X16_WCD_A_ANALOG_INT_EN_SET,
+				MSM89XX_PMIC_ANALOG_INT_EN_SET,
 				(0x01 << (irq - 8)), 0x00);
 		snd_soc_update_bits(map.codec,
-				MSM8X16_WCD_A_ANALOG_INT_EN_CLR,
+				MSM89XX_PMIC_ANALOG_INT_EN_CLR,
 				(0x01 << (irq - 8)), (0x01 << (irq - 8)));
 	}
 
@@ -161,10 +161,6 @@ int wcd9xxx_spmi_request_irq(int irq, irq_handler_t handler,
 	int rc;
 	unsigned long irq_flags;
 
-	map.linuxirq[irq] =
-		spmi_get_irq_byname(map.spmi[BIT_BYTE(irq)], NULL,
-				    irq_names[irq]);
-
 	if (strcmp(name, "mbhc sw intr"))
 		irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
 			IRQF_ONESHOT;
@@ -234,7 +230,7 @@ static irqreturn_t wcd9xxx_spmi_irq_handler(int linux_irq, void *data)
 	for (i = 0; i < NUM_IRQ_REGS; i++) {
 		status[i] |= snd_soc_read(map.codec,
 				BIT_BYTE(irq) * 0x100 +
-			MSM8X16_WCD_A_DIGITAL_INT_LATCHED_STS);
+			MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS);
 		status[i] &= ~map.mask[i];
 	}
 	for (i = 0; i < MAX_NUM_IRQS; i++) {
@@ -418,10 +414,10 @@ void wcd9xxx_spmi_set_codec(struct snd_soc_codec *codec)
 	map.codec = codec;
 }
 
-void wcd9xxx_spmi_set_dev(struct platform_device *pdev, int i)
+void wcd9xxx_spmi_set_dev(struct spmi_device *spmi, int i)
 {
 	if (i < NUM_IRQ_REGS)
-		map.spmi[i] = pdev;
+		map.spmi[i] = spmi;
 }
 
 int wcd9xxx_spmi_irq_init(void)

sound/soc/codecs/msm8x16/msm89xx-regmap.c

@@ -0,0 +1,417 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "msm8x16-wcd.h"
+
+/*
+ * Default register reset values that are common across different versions
+ * are defined here. If a register reset value is changed based on version
+ * then remove it from this structure and add it in version specific
+ * structures.
+ */
+static struct reg_default
+	msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE] = {
+	{MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x13},
+	{MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 0x13},
+	{MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CLK_OTHR_CTL, 0x04},
+	{MSM89XX_CDC_CORE_CLK_RX_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CLK_SD_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CLK_WSA_VI_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX1_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX2_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX3_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX1_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX2_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX3_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX1_B3_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX2_B3_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX3_B3_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX1_B4_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX2_B4_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX3_B4_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX1_B5_CTL, 0x68},
+	{MSM89XX_CDC_CORE_RX2_B5_CTL, 0x68},
+	{MSM89XX_CDC_CORE_RX3_B5_CTL, 0x68},
+	{MSM89XX_CDC_CORE_RX1_B6_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX2_B6_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX3_B6_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_TOP_GAIN_UPDATE, 0x00},
+	{MSM89XX_CDC_CORE_TOP_CTL, 0x01},
+	{MSM89XX_CDC_CORE_COMP0_B1_CTL, 0x30},
+	{MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xB5},
+	{MSM89XX_CDC_CORE_COMP0_B3_CTL, 0x28},
+	{MSM89XX_CDC_CORE_COMP0_B4_CTL, 0x37},
+	{MSM89XX_CDC_CORE_COMP0_B5_CTL, 0x7F},
+	{MSM89XX_CDC_CORE_COMP0_B6_CTL, 0x00},
+	{MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS, 0x03},
+	{MSM89XX_CDC_CORE_COMP0_FS_CFG, 0x03},
+	{MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL, 0x02},
+	{MSM89XX_CDC_CORE_DEBUG_DESER1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_DEBUG_DESER2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG, 0x00},
+	{MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG, 0x00},
+	{MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG, 0x00},
+	{MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR1_CTL, 0x40},
+	{MSM89XX_CDC_CORE_IIR2_CTL, 0x40},
+	{MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_RX2_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_RX3_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_TX_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL, 0x00},
+	{MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL, 0x00},
+	{MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER, 0x00},
+	{MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER, 0x00},
+	{MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER, 0x00},
+	{MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER, 0x00},
+	{MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, 0x00},
+	{MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, 0x00},
+	{MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, 0x00},
+	{MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, 0x00},
+	{MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG, 0x00},
+	{MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG, 0x00},
+	{MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG, 0x00},
+	{MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG, 0x00},
+	{MSM89XX_CDC_CORE_TX1_MUX_CTL, 0x00},
+	{MSM89XX_CDC_CORE_TX2_MUX_CTL, 0x00},
+	{MSM89XX_CDC_CORE_TX3_MUX_CTL, 0x00},
+	{MSM89XX_CDC_CORE_TX4_MUX_CTL, 0x00},
+	{MSM89XX_CDC_CORE_TX1_CLK_FS_CTL, 0x03},
+	{MSM89XX_CDC_CORE_TX2_CLK_FS_CTL, 0x03},
+	{MSM89XX_CDC_CORE_TX3_CLK_FS_CTL, 0x03},
+	{MSM89XX_CDC_CORE_TX4_CLK_FS_CTL, 0x03},
+	{MSM89XX_CDC_CORE_TX1_DMIC_CTL, 0x00},
+	{MSM89XX_CDC_CORE_TX2_DMIC_CTL, 0x00},
+	{MSM89XX_CDC_CORE_TX3_DMIC_CTL, 0x00},
+	{MSM89XX_CDC_CORE_TX4_DMIC_CTL, 0x00},
+};
+
+static struct reg_default
+	msm89xx_pmic_cdc_defaults[MSM89XX_PMIC_CDC_CACHE_SIZE] = {
+	{MSM89XX_PMIC_DIGITAL_REVISION1, 0x00},
+	{MSM89XX_PMIC_DIGITAL_REVISION2, 0x00},
+	{MSM89XX_PMIC_DIGITAL_PERPH_TYPE, 0x23},
+	{MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE, 0x01},
+	{MSM89XX_PMIC_DIGITAL_INT_RT_STS, 0x00},
+	{MSM89XX_PMIC_DIGITAL_INT_SET_TYPE, 0xFF},
+	{MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH, 0xFF},
+	{MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW, 0x00},
+	{MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR, 0x00},
+	{MSM89XX_PMIC_DIGITAL_INT_EN_SET, 0x00},
+	{MSM89XX_PMIC_DIGITAL_INT_EN_CLR, 0x00},
+	{MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS, 0x00},
+	{MSM89XX_PMIC_DIGITAL_INT_PENDING_STS, 0x00},
+	{MSM89XX_PMIC_DIGITAL_INT_MID_SEL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_INT_PRIORITY, 0x00},
+	{MSM89XX_PMIC_DIGITAL_GPIO_MODE, 0x00},
+	{MSM89XX_PMIC_DIGITAL_PIN_CTL_OE, 0x01},
+	{MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA, 0x00},
+	{MSM89XX_PMIC_DIGITAL_PIN_STATUS, 0x00},
+	{MSM89XX_PMIC_DIGITAL_HDRIVE_CTL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL, 0x02},
+	{MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL, 0x02},
+	{MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1, 0x7C},
+	{MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2, 0x7C},
+	{MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3, 0x7C},
+	{MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0, 0x00},
+	{MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1, 0x00},
+	{MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2, 0x00},
+	{MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3, 0x00},
+	{MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN, 0x00},
+	{MSM89XX_PMIC_DIGITAL_SPARE_0, 0x00},
+	{MSM89XX_PMIC_DIGITAL_SPARE_1, 0x00},
+	{MSM89XX_PMIC_DIGITAL_SPARE_2, 0x00},
+	{MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0x00},
+	{MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1, 0x00},
+	{MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2, 0x02},
+	{MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x05},
+	{MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4, 0x00},
+	{MSM89XX_PMIC_DIGITAL_INT_TEST1, 0x00},
+	{MSM89XX_PMIC_DIGITAL_INT_TEST_VAL, 0x00},
+	{MSM89XX_PMIC_DIGITAL_TRIM_NUM, 0x00},
+	{MSM89XX_PMIC_DIGITAL_TRIM_CTRL, 0x00},
+	{MSM89XX_PMIC_ANALOG_REVISION1, 0x00},
+	{MSM89XX_PMIC_ANALOG_REVISION2, 0x00},
+	{MSM89XX_PMIC_ANALOG_REVISION3, 0x00},
+	{MSM89XX_PMIC_ANALOG_REVISION4, 0x00},
+	{MSM89XX_PMIC_ANALOG_PERPH_TYPE, 0x23},
+	{MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE, 0x09},
+	{MSM89XX_PMIC_ANALOG_INT_RT_STS, 0x00},
+	{MSM89XX_PMIC_ANALOG_INT_SET_TYPE, 0x3F},
+	{MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH, 0x3F},
+	{MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW, 0x00},
+	{MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR, 0x00},
+	{MSM89XX_PMIC_ANALOG_INT_EN_SET, 0x00},
+	{MSM89XX_PMIC_ANALOG_INT_EN_CLR, 0x00},
+	{MSM89XX_PMIC_ANALOG_INT_LATCHED_STS, 0x00},
+	{MSM89XX_PMIC_ANALOG_INT_PENDING_STS, 0x00},
+	{MSM89XX_PMIC_ANALOG_INT_MID_SEL, 0x00},
+	{MSM89XX_PMIC_ANALOG_INT_PRIORITY, 0x00},
+	{MSM89XX_PMIC_ANALOG_MICB_1_EN, 0x00},
+	{MSM89XX_PMIC_ANALOG_MICB_1_VAL, 0x20},
+	{MSM89XX_PMIC_ANALOG_MICB_1_CTL, 0x00},
+	{MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS, 0x49},
+	{MSM89XX_PMIC_ANALOG_MICB_2_EN, 0x20},
+	{MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2, 0x00},
+	{MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x00},
+	{MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x35},
+	{MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x08},
+	{MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x00},
+	{MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, 0x98},
+	{MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, 0x00},
+	{MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL, 0x20},
+	{MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL, 0x40},
+	{MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL, 0x61},
+	{MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL, 0x80},
+	{MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT, 0x00},
+	{MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x00},
+	{MSM89XX_PMIC_ANALOG_TX_1_EN, 0x03},
+	{MSM89XX_PMIC_ANALOG_TX_2_EN, 0x03},
+	{MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1, 0xBF},
+	{MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2, 0x8C},
+	{MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL, 0x00},
+	{MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x6B},
+	{MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV, 0x51},
+	{MSM89XX_PMIC_ANALOG_TX_3_EN, 0x02},
+	{MSM89XX_PMIC_ANALOG_NCP_EN, 0x26},
+	{MSM89XX_PMIC_ANALOG_NCP_CLK, 0x23},
+	{MSM89XX_PMIC_ANALOG_NCP_DEGLITCH, 0x5B},
+	{MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x08},
+	{MSM89XX_PMIC_ANALOG_NCP_BIAS, 0x29},
+	{MSM89XX_PMIC_ANALOG_NCP_VCTRL, 0x24},
+	{MSM89XX_PMIC_ANALOG_NCP_TEST, 0x00},
+	{MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR, 0xD5},
+	{MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER, 0xE8},
+	{MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL, 0xCF},
+	{MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT, 0x6E},
+	{MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x18},
+	{MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA, 0x5A},
+	{MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP, 0x69},
+	{MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP, 0x29},
+	{MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x80},
+	{MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL, 0xDA},
+	{MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0x16},
+	{MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x00},
+	{MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x20},
+	{MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x00},
+	{MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x20},
+	{MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x12},
+	{MSM89XX_PMIC_ANALOG_RX_ATEST, 0x00},
+	{MSM89XX_PMIC_ANALOG_RX_HPH_STATUS, 0x0C},
+	{MSM89XX_PMIC_ANALOG_RX_EAR_STATUS, 0x00},
+	{MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x00},
+	{MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x00},
+	{MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x83},
+	{MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET, 0x91},
+	{MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x29},
+	{MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET, 0x4D},
+	{MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1},
+	{MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x1E},
+	{MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC, 0xCB},
+	{MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x00},
+	{MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x02},
+	{MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE, 0x14},
+	{MSM89XX_PMIC_ANALOG_BYPASS_MODE, 0x00},
+	{MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, 0x1F},
+	{MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO, 0x8C},
+	{MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE, 0xC0},
+	{MSM89XX_PMIC_ANALOG_BOOST_TEST1_1, 0x00},
+	{MSM89XX_PMIC_ANALOG_BOOST_TEST_2, 0x00},
+	{MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS, 0x00},
+	{MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS, 0x00},
+	{MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR, 0x00},
+	{MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL, 0x00},
+	{MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0x00},
+	{MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1, 0x00},
+	{MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2, 0x01},
+	{MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x05},
+	{MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4, 0x00},
+	{MSM89XX_PMIC_ANALOG_INT_TEST1, 0x00},
+	{MSM89XX_PMIC_ANALOG_INT_TEST_VAL, 0x00},
+	{MSM89XX_PMIC_ANALOG_TRIM_NUM, 0x04},
+	{MSM89XX_PMIC_ANALOG_TRIM_CTRL1, 0x00},
+	{MSM89XX_PMIC_ANALOG_TRIM_CTRL2, 0x00},
+	{MSM89XX_PMIC_ANALOG_TRIM_CTRL3, 0x00},
+	{MSM89XX_PMIC_ANALOG_TRIM_CTRL4, 0x00},
+};
+
+static bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg)
+{
+	return msm89xx_cdc_core_reg_readable[reg];
+}
+
+static bool msm89xx_pmic_cdc_readable_reg(struct device *dev, unsigned int reg)
+{
+	return msm89xx_pmic_cdc_reg_readable[reg];
+}
+
+static bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case MSM89XX_CDC_CORE_RX1_B1_CTL:
+	case MSM89XX_CDC_CORE_RX2_B1_CTL:
+	case MSM89XX_CDC_CORE_RX3_B1_CTL:
+	case MSM89XX_CDC_CORE_RX1_B6_CTL:
+	case MSM89XX_CDC_CORE_RX2_B6_CTL:
+	case MSM89XX_CDC_CORE_RX3_B6_CTL:
+	case MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG:
+	case MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG:
+	case MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL:
+	case MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL:
+	case MSM89XX_CDC_CORE_CLK_MCLK_CTL:
+	case MSM89XX_CDC_CORE_CLK_PDM_CTL:
+	case MSM89XX_PMIC_ANALOG_BYPASS_MODE:
+	case MSM89XX_PMIC_ANALOG_BOOST_EN_CTL:
+	case MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL:
+	case MSM89XX_PMIC_ANALOG_CURRENT_LIMIT:
+	case MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL:
+	case MSM89XX_PMIC_ANALOG_NCP_FBCTRL:
+	case MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool msm89xx_pmic_cdc_volatile_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case MSM89XX_PMIC_DIGITAL_REVISION1:
+	case MSM89XX_PMIC_DIGITAL_REVISION2:
+	case MSM89XX_PMIC_DIGITAL_PERPH_TYPE:
+	case MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE:
+	case MSM89XX_PMIC_DIGITAL_INT_RT_STS:
+	case MSM89XX_PMIC_DIGITAL_INT_SET_TYPE:
+	case MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH:
+	case MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW:
+	case MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS:
+	case MSM89XX_PMIC_DIGITAL_INT_PENDING_STS:
+	case MSM89XX_PMIC_DIGITAL_PIN_STATUS:
+	case MSM89XX_PMIC_DIGITAL_SEC_ACCESS:
+	case MSM89XX_PMIC_ANALOG_SEC_ACCESS:
+	case MSM89XX_PMIC_ANALOG_REVISION1:
+	case MSM89XX_PMIC_ANALOG_REVISION2:
+	case MSM89XX_PMIC_ANALOG_REVISION3:
+	case MSM89XX_PMIC_ANALOG_REVISION4:
+	case MSM89XX_PMIC_ANALOG_PERPH_TYPE:
+	case MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE:
+	case MSM89XX_PMIC_ANALOG_INT_RT_STS:
+	case MSM89XX_PMIC_ANALOG_INT_SET_TYPE:
+	case MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH:
+	case MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW:
+	case MSM89XX_PMIC_ANALOG_INT_LATCHED_STS:
+	case MSM89XX_PMIC_ANALOG_INT_PENDING_STS:
+	case MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT:
+	case MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT:
+	case MSM89XX_PMIC_ANALOG_RX_HPH_STATUS:
+	case MSM89XX_PMIC_ANALOG_RX_EAR_STATUS:
+	case MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS:
+	case MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS:
+		return true;
+	default:
+		return false;
+	}
+}
+
+struct regmap_config msm89xx_pmic_cdc_regmap_config = {
+	.reg_bits	= 16,
+	.val_bits	= 8,
+	.max_register	= MSM89XX_PMIC_CDC_CACHE_SIZE,
+	.fast_io	= true,
+	.reg_defaults = msm89xx_pmic_cdc_defaults,
+	.num_reg_defaults = ARRAY_SIZE(msm89xx_pmic_cdc_defaults),
+	.readable_reg = msm89xx_pmic_cdc_readable_reg,
+	.volatile_reg = msm89xx_pmic_cdc_volatile_reg,
+	.cache_type = REGCACHE_RBTREE,
+	.reg_format_endian = REGMAP_ENDIAN_NATIVE,
+	.val_format_endian = REGMAP_ENDIAN_NATIVE,
+	.can_multi_write = true,
+	.lock = enable_digital_callback,
+	.unlock = disable_digital_callback,
+
+};
+
+struct regmap_config msm89xx_cdc_core_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+
+	.max_register = MSM89XX_CDC_CORE_CACHE_SIZE,
+	.reg_defaults = msm89xx_cdc_core_defaults,
+	.num_reg_defaults = ARRAY_SIZE(msm89xx_cdc_core_defaults),
+	.readable_reg = msm89xx_cdc_core_readable_reg,
+	.volatile_reg = msm89xx_cdc_core_volatile_reg,
+	.cache_type = REGCACHE_RBTREE,
+	.reg_format_endian = REGMAP_ENDIAN_NATIVE,
+	.val_format_endian = REGMAP_ENDIAN_NATIVE,
+	.can_multi_write = true,
+};

sound/soc/codecs/msm8x16/msm8x16-wcd-tables.c

@@ -0,0 +1,263 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "msm8x16-wcd.h"
+
+const u8 msm89xx_pmic_cdc_reg_readable[MSM89XX_PMIC_CDC_CACHE_SIZE] = {
+		[MSM89XX_PMIC_DIGITAL_REVISION1] = 1,
+		[MSM89XX_PMIC_DIGITAL_REVISION2] = 1,
+		[MSM89XX_PMIC_DIGITAL_PERPH_TYPE] = 1,
+		[MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE] = 1,
+		[MSM89XX_PMIC_DIGITAL_INT_RT_STS] = 1,
+		[MSM89XX_PMIC_DIGITAL_INT_SET_TYPE] = 1,
+		[MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH] = 1,
+		[MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW] = 1,
+		[MSM89XX_PMIC_DIGITAL_INT_EN_SET] = 1,
+		[MSM89XX_PMIC_DIGITAL_INT_EN_CLR] = 1,
+		[MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS] = 1,
+		[MSM89XX_PMIC_DIGITAL_INT_PENDING_STS] = 1,
+		[MSM89XX_PMIC_DIGITAL_INT_MID_SEL] = 1,
+		[MSM89XX_PMIC_DIGITAL_INT_PRIORITY] = 1,
+		[MSM89XX_PMIC_DIGITAL_GPIO_MODE] = 1,
+		[MSM89XX_PMIC_DIGITAL_PIN_CTL_OE] = 1,
+		[MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA] = 1,
+		[MSM89XX_PMIC_DIGITAL_PIN_STATUS] = 1,
+		[MSM89XX_PMIC_DIGITAL_HDRIVE_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_RST_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2] = 1,
+		[MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3] = 1,
+		[MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0] = 1,
+		[MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1] = 1,
+		[MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2] = 1,
+		[MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3] = 1,
+		[MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_SPARE_0] = 1,
+		[MSM89XX_PMIC_DIGITAL_SPARE_1] = 1,
+		[MSM89XX_PMIC_DIGITAL_SPARE_2] = 1,
+		[MSM89XX_PMIC_ANALOG_REVISION1] = 1,
+		[MSM89XX_PMIC_ANALOG_REVISION2] = 1,
+		[MSM89XX_PMIC_ANALOG_REVISION3] = 1,
+		[MSM89XX_PMIC_ANALOG_REVISION4] = 1,
+		[MSM89XX_PMIC_ANALOG_PERPH_TYPE] = 1,
+		[MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE] = 1,
+		[MSM89XX_PMIC_ANALOG_INT_RT_STS] = 1,
+		[MSM89XX_PMIC_ANALOG_INT_SET_TYPE] = 1,
+		[MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH] = 1,
+		[MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW] = 1,
+		[MSM89XX_PMIC_ANALOG_INT_EN_SET] = 1,
+		[MSM89XX_PMIC_ANALOG_INT_EN_CLR] = 1,
+		[MSM89XX_PMIC_ANALOG_INT_LATCHED_STS] = 1,
+		[MSM89XX_PMIC_ANALOG_INT_PENDING_STS] = 1,
+		[MSM89XX_PMIC_ANALOG_INT_MID_SEL] = 1,
+		[MSM89XX_PMIC_ANALOG_INT_PRIORITY] = 1,
+		[MSM89XX_PMIC_ANALOG_MICB_1_EN] = 1,
+		[MSM89XX_PMIC_ANALOG_MICB_1_VAL] = 1,
+		[MSM89XX_PMIC_ANALOG_MICB_1_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS] = 1,
+		[MSM89XX_PMIC_ANALOG_MICB_2_EN] = 1,
+		[MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2] = 1,
+		[MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1] = 1,
+		[MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2] = 1,
+		[MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER] = 1,
+		[MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT] = 1,
+		[MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT] = 1,
+		[MSM89XX_PMIC_ANALOG_TX_1_EN] = 1,
+		[MSM89XX_PMIC_ANALOG_TX_2_EN] = 1,
+		[MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1] = 1,
+		[MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2] = 1,
+		[MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS] = 1,
+		[MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV] = 1,
+		[MSM89XX_PMIC_ANALOG_TX_3_EN] = 1,
+		[MSM89XX_PMIC_ANALOG_NCP_EN] = 1,
+		[MSM89XX_PMIC_ANALOG_NCP_CLK] = 1,
+		[MSM89XX_PMIC_ANALOG_NCP_DEGLITCH] = 1,
+		[MSM89XX_PMIC_ANALOG_NCP_FBCTRL] = 1,
+		[MSM89XX_PMIC_ANALOG_NCP_BIAS] = 1,
+		[MSM89XX_PMIC_ANALOG_NCP_VCTRL] = 1,
+		[MSM89XX_PMIC_ANALOG_NCP_TEST] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_EAR_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_ATEST] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_HPH_STATUS] = 1,
+		[MSM89XX_PMIC_ANALOG_RX_EAR_STATUS] = 1,
+		[MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET] = 1,
+		[MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET] = 1,
+		[MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC] = 1,
+		[MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG] = 1,
+		[MSM89XX_PMIC_ANALOG_CURRENT_LIMIT] = 1,
+		[MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE] = 1,
+		[MSM89XX_PMIC_ANALOG_BYPASS_MODE] = 1,
+		[MSM89XX_PMIC_ANALOG_BOOST_EN_CTL] = 1,
+		[MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO] = 1,
+		[MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE] = 1,
+		[MSM89XX_PMIC_ANALOG_BOOST_TEST1_1] = 1,
+		[MSM89XX_PMIC_ANALOG_BOOST_TEST_2] = 1,
+		[MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS] = 1,
+		[MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS] = 1,
+		[MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR] = 1,
+		[MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL] = 1,
+		[MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL] = 1,
+		[MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR] = 1,
+		[MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR] = 1,
+		[MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR] = 1,
+		[MSM89XX_PMIC_DIGITAL_SEC_ACCESS] = 1,
+		[MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3] = 1,
+		[MSM89XX_PMIC_ANALOG_SEC_ACCESS] = 1,
+};
+
+const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE] = {
+		[MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1,
+		[MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1,
+		[MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1,
+		[MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1,
+		[MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1,
+		[MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1,
+		[MSM89XX_CDC_CORE_CLK_SD_CTL] = 1,
+		[MSM89XX_CDC_CORE_CLK_WSA_VI_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX1_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX2_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX3_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX1_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX2_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX3_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX1_B3_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX2_B3_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX3_B3_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX1_B4_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX2_B4_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX3_B4_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX1_B5_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX2_B5_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX3_B5_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX1_B6_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX2_B6_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX3_B6_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1,
+		[MSM89XX_CDC_CORE_TOP_CTL] = 1,
+		[MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1,
+		[MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1,
+		[MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1,
+		[MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1,
+		[MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1,
+		[MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR1_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR2_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1,
+		[MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1,
+		[MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1,
+		[MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1,
+		[MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1,
+		[MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1,
+		[MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1,
+		[MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1,
+		[MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1,
+		[MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1,
+		[MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1,
+		[MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1,
+		[MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1,
+		[MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1,
+		[MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1,
+		[MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1,
+		[MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1,
+		[MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1,
+		[MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1,
+		[MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1,
+		[MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1,
+		[MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1,
+		[MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1,
+		[MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1,
+		[MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1,
+		[MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1,
+};

sound/soc/codecs/msm8x16/msm8x16-wcd.h

@@ -0,0 +1,341 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef MSM8X16_WCD_H
+#define MSM8X16_WCD_H
+
+#include <sound/soc.h>
+#include <sound/jack.h>
+#include <sound/q6afe-v2.h>
+#include "../wcd-mbhc-v2.h"
+#include "../wcdcal-hwdep.h"
+#include "msm8x16_wcd_registers.h"
+
+#define MICBIAS_EXT_BYP_CAP 0x00
+#define MICBIAS_NO_EXT_BYP_CAP 0x01
+
+#define MSM89XX_NUM_IRQ_REGS	2
+#define MAX_REGULATOR				7
+#define MSM89XX_REG_VAL(reg, val)		{reg, 0, val}
+#define MSM8X16_TOMBAK_LPASS_AUDIO_CORE_DIG_CODEC_CLK_SEL	0xFE03B004
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_CMD_RCGR			0x0181C09C
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_CFG_RCGR			0x0181C0A0
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_M				0x0181C0A4
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_N				0x0181C0A8
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_D				0x0181C0AC
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_CBCR			0x0181C0B0
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_AHB_CBCR			0x0181C0B4
+
+#define MSM8X16_CODEC_NAME "msm8x16_wcd_codec"
+
+#define MSM89XX_IS_CDC_CORE_REG(reg) \
+	(((reg >= 0x00) && (reg <= 0x3FF)) ? 1 : 0)
+#define MSM89XX_IS_PMIC_CDC_REG(reg) \
+	(((reg >= 0xF000) && (reg <= 0xF1FF)) ? 1 : 0)
+/*
+ * MCLK activity indicators during suspend and resume call
+ */
+#define MCLK_SUS_DIS	1
+#define MCLK_SUS_RSC	2
+#define MCLK_SUS_NO_ACT	3
+
+#define NUM_DECIMATORS	4
+#define MSM89XX_VDD_SPKDRV_NAME "cdc-vdd-spkdrv"
+
+#define DEFAULT_MULTIPLIER 800
+#define DEFAULT_GAIN 9
+#define DEFAULT_OFFSET 100
+
+extern const u8 msm89xx_pmic_cdc_reg_readable[MSM89XX_PMIC_CDC_CACHE_SIZE];
+extern const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE];
+extern struct regmap_config msm89xx_cdc_core_regmap_config;
+extern struct regmap_config msm89xx_pmic_cdc_regmap_config;
+
+enum codec_versions {
+	TOMBAK_1_0,
+	TOMBAK_2_0,
+	CONGA,
+	CAJON,
+	CAJON_2_0,
+	DIANGU,
+	UNSUPPORTED,
+};
+
+/* Support different hph modes */
+enum {
+	NORMAL_MODE = 0,
+	HD2_MODE,
+};
+
+/* Codec supports 1 compander */
+enum {
+	COMPANDER_NONE = 0,
+	COMPANDER_1, /* HPHL/R */
+	COMPANDER_MAX,
+};
+
+enum wcd_curr_ref {
+	I_h4_UA = 0,
+	I_pt5_UA,
+	I_14_UA,
+	I_l4_UA,
+	I_1_UA,
+};
+
+enum wcd_mbhc_imp_det_pin {
+	WCD_MBHC_DET_NONE = 0,
+	WCD_MBHC_DET_HPHL,
+	WCD_MBHC_DET_HPHR,
+	WCD_MBHC_DET_BOTH,
+};
+
+
+/* Each micbias can be assigned to one of three cfilters
+ * Vbatt_min >= .15V + ldoh_v
+ * ldoh_v >= .15v + cfiltx_mv
+ * If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv
+ * If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv
+ * If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv
+ * If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv
+ */
+
+struct wcd9xxx_micbias_setting {
+	u8 ldoh_v;
+	u32 cfilt1_mv; /* in mv */
+	u32 cfilt2_mv; /* in mv */
+	u32 cfilt3_mv; /* in mv */
+	/* Different WCD9xxx series codecs may not
+	 * have 4 mic biases. If a codec has fewer
+	 * mic biases, some of these properties will
+	 * not be used.
+	 */
+	u8 bias1_cfilt_sel;
+	u8 bias2_cfilt_sel;
+	u8 bias3_cfilt_sel;
+	u8 bias4_cfilt_sel;
+	u8 bias1_cap_mode;
+	u8 bias2_cap_mode;
+	u8 bias3_cap_mode;
+	u8 bias4_cap_mode;
+	bool bias2_is_headset_only;
+};
+
+enum msm8x16_wcd_pid_current {
+	MSM89XX_PID_MIC_2P5_UA,
+	MSM89XX_PID_MIC_5_UA,
+	MSM89XX_PID_MIC_10_UA,
+	MSM89XX_PID_MIC_20_UA,
+};
+
+struct msm8x16_wcd_reg_mask_val {
+	u16	reg;
+	u8	mask;
+	u8	val;
+};
+
+enum msm8x16_wcd_mbhc_analog_pwr_cfg {
+	MSM89XX_ANALOG_PWR_COLLAPSED = 0,
+	MSM89XX_ANALOG_PWR_ON,
+	MSM89XX_NUM_ANALOG_PWR_CONFIGS,
+};
+
+/* Number of input and output I2S port */
+enum {
+	MSM89XX_RX1 = 0,
+	MSM89XX_RX2,
+	MSM89XX_RX3,
+	MSM89XX_RX_MAX,
+};
+
+enum {
+	MSM89XX_TX1 = 0,
+	MSM89XX_TX2,
+	MSM89XX_TX3,
+	MSM89XX_TX4,
+	MSM89XX_TX_MAX,
+};
+
+enum {
+	/* INTR_REG 0 - Digital Periph */
+	MSM89XX_IRQ_SPKR_CNP = 0,
+	MSM89XX_IRQ_SPKR_CLIP,
+	MSM89XX_IRQ_SPKR_OCP,
+	MSM89XX_IRQ_MBHC_INSREM_DET1,
+	MSM89XX_IRQ_MBHC_RELEASE,
+	MSM89XX_IRQ_MBHC_PRESS,
+	MSM89XX_IRQ_MBHC_INSREM_DET,
+	MSM89XX_IRQ_MBHC_HS_DET,
+	/* INTR_REG 1 - Analog Periph */
+	MSM89XX_IRQ_EAR_OCP,
+	MSM89XX_IRQ_HPHR_OCP,
+	MSM89XX_IRQ_HPHL_OCP,
+	MSM89XX_IRQ_EAR_CNP,
+	MSM89XX_IRQ_HPHR_CNP,
+	MSM89XX_IRQ_HPHL_CNP,
+	MSM89XX_NUM_IRQS,
+};
+
+enum {
+	ON_DEMAND_MICBIAS = 0,
+	ON_DEMAND_SPKDRV,
+	ON_DEMAND_SUPPLIES_MAX,
+};
+
+/*
+ * The delay list is per codec HW specification.
+ * Please add delay in the list in the future instead
+ * of magic number
+ */
+enum {
+	CODEC_DELAY_1_MS = 1000,
+	CODEC_DELAY_1_1_MS  = 1100,
+};
+
+struct msm8x16_wcd_regulator {
+	const char *name;
+	int min_uv;
+	int max_uv;
+	int optimum_ua;
+	bool ondemand;
+	struct regulator *regulator;
+};
+
+struct on_demand_supply {
+	struct regulator *supply;
+	atomic_t ref;
+};
+
+struct wcd_imped_i_ref {
+	enum wcd_curr_ref curr_ref;
+	int min_val;
+	int multiplier;
+	int gain_adj;
+	int offset;
+};
+
+struct msm8916_asoc_mach_data {
+	int codec_type;
+	int ext_pa;
+	int us_euro_gpio;
+	int spk_ext_pa_gpio;
+	int mclk_freq;
+	int lb_mode;
+	int afe_clk_ver;
+	u8 micbias1_cap_mode;
+	u8 micbias2_cap_mode;
+	atomic_t mclk_rsc_ref;
+	atomic_t mclk_enabled;
+	atomic_t wsa_mclk_rsc_ref;
+	struct mutex cdc_mclk_mutex;
+	struct mutex wsa_mclk_mutex;
+	struct delayed_work disable_mclk_work;
+	struct afe_digital_clk_cfg digital_cdc_clk;
+	struct afe_clk_set digital_cdc_core_clk;
+	void __iomem *vaddr_gpio_mux_spkr_ctl;
+	void __iomem *vaddr_gpio_mux_mic_ctl;
+	void __iomem *vaddr_gpio_mux_quin_ctl;
+	void __iomem *vaddr_gpio_mux_pcm_ctl;
+	struct on_demand_supply wsa_switch_supply;
+};
+
+struct msm8x16_wcd_pdata {
+	int irq;
+	int irq_base;
+	int num_irqs;
+	int reset_gpio;
+	void *msm8x16_wcd_ahb_base_vaddr;
+	struct wcd9xxx_micbias_setting micbias;
+	struct msm8x16_wcd_regulator regulator[MAX_REGULATOR];
+	u32 mclk_rate;
+	u32 is_lpass;
+};
+
+enum msm8x16_wcd_micbias_num {
+	MSM89XX_MICBIAS1 = 0,
+};
+
+struct msm8x16_wcd {
+	struct device *dev;
+	struct mutex io_lock;
+	u8 version;
+
+	int reset_gpio;
+	int (*read_dev)(struct snd_soc_codec *codec,
+			unsigned short reg);
+	int (*write_dev)(struct snd_soc_codec *codec,
+			 unsigned short reg, u8 val);
+
+	u32 num_of_supplies;
+	struct regulator_bulk_data *supplies;
+
+	u8 idbyte[4];
+
+	int num_irqs;
+	u32 mclk_rate;
+};
+
+struct msm8x16_wcd_priv {
+	struct snd_soc_codec *codec;
+	u16 pmic_rev;
+	u16 codec_version;
+	u32 boost_voltage;
+	u32 adc_count;
+	u32 rx_bias_count;
+	s32 dmic_1_2_clk_cnt;
+	u32 mute_mask;
+	bool mclk_enabled;
+	bool clock_active;
+	bool config_mode_active;
+	u16 boost_option;
+	/* mode to select hd2 */
+	u32 hph_mode;
+	/* compander used for each rx chain */
+	u32 comp_enabled[MSM89XX_RX_MAX];
+	bool spk_boost_set;
+	bool ear_pa_boost_set;
+	bool ext_spk_boost_set;
+	bool dec_active[NUM_DECIMATORS];
+	struct on_demand_supply on_demand_list[ON_DEMAND_SUPPLIES_MAX];
+	struct regulator *spkdrv_reg;
+	/* mbhc module */
+	struct wcd_mbhc mbhc;
+	/* cal info for codec */
+	struct fw_info *fw_data;
+	struct blocking_notifier_head notifier;
+	int (*codec_spk_ext_pa_cb)(struct snd_soc_codec *codec, int enable);
+	int (*codec_hph_comp_gpio)(bool enable);
+	unsigned long status_mask;
+	struct wcd_imped_i_ref imped_i_ref;
+	enum wcd_mbhc_imp_det_pin imped_det_pin;
+};
+
+extern int msm8x16_wcd_mclk_enable(struct snd_soc_codec *codec, int mclk_enable,
+			     bool dapm);
+
+extern int msm8x16_wcd_hs_detect(struct snd_soc_codec *codec,
+		    struct wcd_mbhc_config *mbhc_cfg);
+
+extern void msm8x16_wcd_hs_detect_exit(struct snd_soc_codec *codec);
+
+extern void msm8x16_update_int_spk_boost(bool enable);
+
+extern void msm8x16_wcd_spk_ext_pa_cb(
+		int (*codec_spk_ext_pa)(struct snd_soc_codec *codec,
+		int enable), struct snd_soc_codec *codec);
+
+extern void msm8x16_wcd_hph_comp_cb(
+		int (*codec_hph_comp_gpio)(bool enable),
+		struct snd_soc_codec *codec);
+void enable_digital_callback(void *flag);
+void disable_digital_callback(void *flag);
+
+#endif
+

sound/soc/codecs/msm8x16/msm8x16_wcd_registers.h

@@ -0,0 +1,585 @@
+ /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef MSM8X16_WCD_REGISTERS_H
+#define MSM8X16_WCD_REGISTERS_H
+
+#define CDC_DIG_BASE		0xF000
+#define CDC_ANA_BASE		0xF100
+
+#define MSM89XX_PMIC_DIGITAL_REVISION1		(CDC_DIG_BASE+0x000)
+#define MSM89XX_PMIC_DIGITAL_REVISION1__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_REVISION2		(CDC_DIG_BASE+0x001)
+#define MSM89XX_PMIC_DIGITAL_REVISION2__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_PERPH_TYPE		(CDC_DIG_BASE+0x004)
+#define MSM89XX_PMIC_DIGITAL_PERPH_TYPE__POR		(0x23)
+#define MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE		(CDC_DIG_BASE+0x005)
+#define MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE__POR		(0x01)
+#define MSM89XX_PMIC_DIGITAL_INT_RT_STS		(CDC_DIG_BASE+0x010)
+#define MSM89XX_PMIC_DIGITAL_INT_RT_STS__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_INT_SET_TYPE		(CDC_DIG_BASE+0x011)
+#define MSM89XX_PMIC_DIGITAL_INT_SET_TYPE__POR		(0xFF)
+#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH		(CDC_DIG_BASE+0x012)
+#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH__POR		(0xFF)
+#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW		(CDC_DIG_BASE+0x013)
+#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR		(CDC_DIG_BASE+0x014)
+#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_INT_EN_SET		(CDC_DIG_BASE+0x015)
+#define MSM89XX_PMIC_DIGITAL_INT_EN_SET__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_INT_EN_CLR		(CDC_DIG_BASE+0x016)
+#define MSM89XX_PMIC_DIGITAL_INT_EN_CLR__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS		(CDC_DIG_BASE+0x018)
+#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_INT_PENDING_STS		(CDC_DIG_BASE+0x019)
+#define MSM89XX_PMIC_DIGITAL_INT_PENDING_STS__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_INT_MID_SEL		(CDC_DIG_BASE+0x01A)
+#define MSM89XX_PMIC_DIGITAL_INT_MID_SEL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_INT_PRIORITY		(CDC_DIG_BASE+0x01B)
+#define MSM89XX_PMIC_DIGITAL_INT_PRIORITY__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_GPIO_MODE		(CDC_DIG_BASE+0x040)
+#define MSM89XX_PMIC_DIGITAL_GPIO_MODE__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_PIN_CTL_OE		(CDC_DIG_BASE+0x041)
+#define MSM89XX_PMIC_DIGITAL_PIN_CTL_OE__POR		(0x01)
+#define MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA		(CDC_DIG_BASE+0x042)
+#define MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_PIN_STATUS		(CDC_DIG_BASE+0x043)
+#define MSM89XX_PMIC_DIGITAL_PIN_STATUS__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_HDRIVE_CTL		(CDC_DIG_BASE+0x044)
+#define MSM89XX_PMIC_DIGITAL_HDRIVE_CTL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_CDC_RST_CTL		(CDC_DIG_BASE+0x046)
+#define MSM89XX_PMIC_DIGITAL_CDC_RST_CTL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL		(CDC_DIG_BASE+0x048)
+#define MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL		(CDC_DIG_BASE+0x049)
+#define MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL		(CDC_DIG_BASE+0x04A)
+#define MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL		(CDC_DIG_BASE+0x050)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL__POR		(0x02)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL		(CDC_DIG_BASE+0x051)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL__POR		(0x02)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL	(CDC_DIG_BASE+0x052)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL		(CDC_DIG_BASE+0x053)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL		(CDC_DIG_BASE+0x054)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL		(CDC_DIG_BASE+0x055)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL	(CDC_DIG_BASE+0x056)
+#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1		(CDC_DIG_BASE+0x058)
+#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1__POR		(0x7C)
+#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2		(CDC_DIG_BASE+0x059)
+#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2__POR		(0x7C)
+#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3		(CDC_DIG_BASE+0x05A)
+#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3__POR		(0x7C)
+#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0		(CDC_DIG_BASE+0x05B)
+#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1		(CDC_DIG_BASE+0x05C)
+#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2		(CDC_DIG_BASE+0x05D)
+#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3		(CDC_DIG_BASE+0x05E)
+#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL		(CDC_DIG_BASE+0x068)
+#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN		(CDC_DIG_BASE+0x069)
+#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_SPARE_0		(CDC_DIG_BASE+0x070)
+#define MSM89XX_PMIC_DIGITAL_SPARE_0__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_SPARE_1		(CDC_DIG_BASE+0x071)
+#define MSM89XX_PMIC_DIGITAL_SPARE_1__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_SPARE_2		(CDC_DIG_BASE+0x072)
+#define MSM89XX_PMIC_DIGITAL_SPARE_2__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_SEC_ACCESS		(CDC_DIG_BASE+0x0D0)
+#define MSM89XX_PMIC_DIGITAL_SEC_ACCESS__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1		(CDC_DIG_BASE+0x0D8)
+#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2		(CDC_DIG_BASE+0x0D9)
+#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2__POR		(0x01)
+#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3		(CDC_DIG_BASE+0x0DA)
+#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3__POR		(0x05)
+#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4		(CDC_DIG_BASE+0x0DB)
+#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_INT_TEST1		(CDC_DIG_BASE+0x0E0)
+#define MSM89XX_PMIC_DIGITAL_INT_TEST1__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_INT_TEST_VAL		(CDC_DIG_BASE+0x0E1)
+#define MSM89XX_PMIC_DIGITAL_INT_TEST_VAL__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_TRIM_NUM		(CDC_DIG_BASE+0x0F0)
+#define MSM89XX_PMIC_DIGITAL_TRIM_NUM__POR		(0x00)
+#define MSM89XX_PMIC_DIGITAL_TRIM_CTRL		(CDC_DIG_BASE+0x0F1)
+#define MSM89XX_PMIC_DIGITAL_TRIM_CTRL__POR		(0x00)
+
+#define MSM89XX_PMIC_ANALOG_REVISION1		(CDC_ANA_BASE+0x00)
+#define MSM89XX_PMIC_ANALOG_REVISION1__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_REVISION2		(CDC_ANA_BASE+0x01)
+#define MSM89XX_PMIC_ANALOG_REVISION2__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_REVISION3		(CDC_ANA_BASE+0x02)
+#define MSM89XX_PMIC_ANALOG_REVISION3__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_REVISION4		(CDC_ANA_BASE+0x03)
+#define MSM89XX_PMIC_ANALOG_REVISION4__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_PERPH_TYPE		(CDC_ANA_BASE+0x04)
+#define MSM89XX_PMIC_ANALOG_PERPH_TYPE__POR		(0x23)
+#define MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE		(CDC_ANA_BASE+0x05)
+#define MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE__POR		(0x09)
+#define MSM89XX_PMIC_ANALOG_INT_RT_STS		(CDC_ANA_BASE+0x10)
+#define MSM89XX_PMIC_ANALOG_INT_RT_STS__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_INT_SET_TYPE		(CDC_ANA_BASE+0x11)
+#define MSM89XX_PMIC_ANALOG_INT_SET_TYPE__POR		(0x3F)
+#define MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH		(CDC_ANA_BASE+0x12)
+#define MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH__POR		(0x3F)
+#define MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW		(CDC_ANA_BASE+0x13)
+#define MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR		(CDC_ANA_BASE+0x14)
+#define MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_INT_EN_SET		(CDC_ANA_BASE+0x15)
+#define MSM89XX_PMIC_ANALOG_INT_EN_SET__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_INT_EN_CLR		(CDC_ANA_BASE+0x16)
+#define MSM89XX_PMIC_ANALOG_INT_EN_CLR__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_INT_LATCHED_STS		(CDC_ANA_BASE+0x18)
+#define MSM89XX_PMIC_ANALOG_INT_LATCHED_STS__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_INT_PENDING_STS		(CDC_ANA_BASE+0x19)
+#define MSM89XX_PMIC_ANALOG_INT_PENDING_STS__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_INT_MID_SEL		(CDC_ANA_BASE+0x1A)
+#define MSM89XX_PMIC_ANALOG_INT_MID_SEL__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_INT_PRIORITY		(CDC_ANA_BASE+0x1B)
+#define MSM89XX_PMIC_ANALOG_INT_PRIORITY__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_MICB_1_EN		(CDC_ANA_BASE+0x40)
+#define MSM89XX_PMIC_ANALOG_MICB_1_EN__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_MICB_1_VAL		(CDC_ANA_BASE+0x41)
+#define MSM89XX_PMIC_ANALOG_MICB_1_VAL__POR		(0x20)
+#define MSM89XX_PMIC_ANALOG_MICB_1_CTL		(CDC_ANA_BASE+0x42)
+#define MSM89XX_PMIC_ANALOG_MICB_1_CTL__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS		(CDC_ANA_BASE+0x43)
+#define MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS__POR		(0x49)
+#define MSM89XX_PMIC_ANALOG_MICB_2_EN		(CDC_ANA_BASE+0x44)
+#define MSM89XX_PMIC_ANALOG_MICB_2_EN__POR		(0x20)
+#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2		(CDC_ANA_BASE+0x45)
+#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL		(CDC_ANA_BASE+0x46)
+#define MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1		(CDC_ANA_BASE+0x47)
+#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1__POR		(0x35)
+#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2		(CDC_ANA_BASE+0x50)
+#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2__POR		(0x08)
+#define MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL		(CDC_ANA_BASE+0x51)
+#define MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER		(CDC_ANA_BASE+0x52)
+#define MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER__POR		(0x98)
+#define MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL	(CDC_ANA_BASE+0x53)
+#define MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL	(CDC_ANA_BASE+0x54)
+#define MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL__POR		(0x20)
+#define MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL	(CDC_ANA_BASE+0x55)
+#define MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL__POR		(0x40)
+#define MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL		(CDC_ANA_BASE+0x56)
+#define MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL__POR		(0x61)
+#define MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL		(CDC_ANA_BASE+0x57)
+#define MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL__POR		(0x80)
+#define MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT		(CDC_ANA_BASE+0x58)
+#define MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT	(CDC_ANA_BASE+0x59)
+#define MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT__POR	(0x00)
+#define MSM89XX_PMIC_ANALOG_TX_1_EN		(CDC_ANA_BASE+0x60)
+#define MSM89XX_PMIC_ANALOG_TX_1_EN__POR		(0x03)
+#define MSM89XX_PMIC_ANALOG_TX_2_EN		(CDC_ANA_BASE+0x61)
+#define MSM89XX_PMIC_ANALOG_TX_2_EN__POR		(0x03)
+#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1		(CDC_ANA_BASE+0x62)
+#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1__POR		(0xBF)
+#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2		(CDC_ANA_BASE+0x63)
+#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2__POR		(0x8C)
+#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL		(CDC_ANA_BASE+0x64)
+#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS		(CDC_ANA_BASE+0x65)
+#define MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS__POR		(0x6B)
+#define MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV		(CDC_ANA_BASE+0x66)
+#define MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV__POR		(0x51)
+#define MSM89XX_PMIC_ANALOG_TX_3_EN		(CDC_ANA_BASE+0x67)
+#define MSM89XX_PMIC_ANALOG_TX_3_EN__POR		(0x02)
+#define MSM89XX_PMIC_ANALOG_NCP_EN		(CDC_ANA_BASE+0x80)
+#define MSM89XX_PMIC_ANALOG_NCP_EN__POR		(0x26)
+#define MSM89XX_PMIC_ANALOG_NCP_CLK		(CDC_ANA_BASE+0x81)
+#define MSM89XX_PMIC_ANALOG_NCP_CLK__POR		(0x23)
+#define MSM89XX_PMIC_ANALOG_NCP_DEGLITCH		(CDC_ANA_BASE+0x82)
+#define MSM89XX_PMIC_ANALOG_NCP_DEGLITCH__POR		(0x5B)
+#define MSM89XX_PMIC_ANALOG_NCP_FBCTRL		(CDC_ANA_BASE+0x83)
+#define MSM89XX_PMIC_ANALOG_NCP_FBCTRL__POR		(0x08)
+#define MSM89XX_PMIC_ANALOG_NCP_BIAS		(CDC_ANA_BASE+0x84)
+#define MSM89XX_PMIC_ANALOG_NCP_BIAS__POR		(0x29)
+#define MSM89XX_PMIC_ANALOG_NCP_VCTRL		(CDC_ANA_BASE+0x85)
+#define MSM89XX_PMIC_ANALOG_NCP_VCTRL__POR		(0x24)
+#define MSM89XX_PMIC_ANALOG_NCP_TEST		(CDC_ANA_BASE+0x86)
+#define MSM89XX_PMIC_ANALOG_NCP_TEST__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR		(CDC_ANA_BASE+0x87)
+#define MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR__POR		(0xD5)
+#define MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER		(CDC_ANA_BASE+0x90)
+#define MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER__POR		(0xE8)
+#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL		(CDC_ANA_BASE+0x91)
+#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL__POR		(0xCF)
+#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT		(CDC_ANA_BASE+0x92)
+#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT__POR		(0x6E)
+#define MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC		(CDC_ANA_BASE+0x93)
+#define MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC__POR		(0x18)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA		(CDC_ANA_BASE+0x94)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA__POR		(0x5A)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP	(CDC_ANA_BASE+0x95)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP__POR		(0x69)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP		(CDC_ANA_BASE+0x96)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP__POR		(0x29)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN		(CDC_ANA_BASE+0x97)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN__POR		(0x80)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL		(CDC_ANA_BASE+0x98)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL__POR		(0xDA)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME		(CDC_ANA_BASE+0x99)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME__POR		(0x16)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST		(CDC_ANA_BASE+0x9A)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL	(CDC_ANA_BASE+0x9B)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL__POR		(0x20)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST		(CDC_ANA_BASE+0x9C)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL	(CDC_ANA_BASE+0x9D)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL__POR		(0x20)
+#define MSM89XX_PMIC_ANALOG_RX_EAR_CTL		(CDC_ANA_BASE+0x9E)
+#define MSM89XX_PMIC_ANALOG_RX_EAR_CTL___POR		(0x12)
+#define MSM89XX_PMIC_ANALOG_RX_ATEST		(CDC_ANA_BASE+0x9F)
+#define MSM89XX_PMIC_ANALOG_RX_ATEST__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_STATUS		(CDC_ANA_BASE+0xA0)
+#define MSM89XX_PMIC_ANALOG_RX_HPH_STATUS__POR		(0x0C)
+#define MSM89XX_PMIC_ANALOG_RX_EAR_STATUS		(CDC_ANA_BASE+0xA1)
+#define MSM89XX_PMIC_ANALOG_RX_EAR_STATUS__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL		(CDC_ANA_BASE+0xAC)
+#define MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL		(CDC_ANA_BASE+0xAD)
+#define MSM89XX_PMIC_ANALOG_RX_RX_LO_EN_CTL__POR	(0x00)
+#define MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL		(CDC_ANA_BASE+0xB0)
+#define MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL__POR		(0x83)
+#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET		(CDC_ANA_BASE+0xB1)
+#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET__POR		(0x91)
+#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL		(CDC_ANA_BASE+0xB2)
+#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL__POR		(0x29)
+#define MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET		(CDC_ANA_BASE+0xB3)
+#define MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET__POR		(0x4D)
+#define MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL		(CDC_ANA_BASE+0xB4)
+#define MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL__POR		(0xE1)
+#define MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL		(CDC_ANA_BASE+0xB5)
+#define MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL__POR		(0x1E)
+#define MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC		(CDC_ANA_BASE+0xB6)
+#define MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC__POR		(0xCB)
+#define MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG		(CDC_ANA_BASE+0xB7)
+#define MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_CURRENT_LIMIT		(CDC_ANA_BASE+0xC0)
+#define MSM89XX_PMIC_ANALOG_CURRENT_LIMIT__POR		(0x02)
+#define MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE		(CDC_ANA_BASE+0xC1)
+#define MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE__POR		(0x14)
+#define MSM89XX_PMIC_ANALOG_BYPASS_MODE		(CDC_ANA_BASE+0xC2)
+#define MSM89XX_PMIC_ANALOG_BYPASS_MODE__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_BOOST_EN_CTL		(CDC_ANA_BASE+0xC3)
+#define MSM89XX_PMIC_ANALOG_BOOST_EN_CTL__POR		(0x1F)
+#define MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO		(CDC_ANA_BASE+0xC4)
+#define MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO__POR		(0x8C)
+#define MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE	(CDC_ANA_BASE+0xC5)
+#define MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE__POR		(0xC0)
+#define MSM89XX_PMIC_ANALOG_BOOST_TEST1_1		(CDC_ANA_BASE+0xC6)
+#define MSM89XX_PMIC_ANALOG_BOOST_TEST1_1__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_BOOST_TEST_2		(CDC_ANA_BASE+0xC7)
+#define MSM89XX_PMIC_ANALOG_BOOST_TEST_2__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS		(CDC_ANA_BASE+0xC8)
+#define MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS		(CDC_ANA_BASE+0xC9)
+#define MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR		(CDC_ANA_BASE+0xCE)
+#define MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL		(CDC_ANA_BASE+0xCF)
+#define MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_SEC_ACCESS		(CDC_ANA_BASE+0xD0)
+#define MSM89XX_PMIC_ANALOG_SEC_ACCESS__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1		(CDC_ANA_BASE+0xD8)
+#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2		(CDC_ANA_BASE+0xD9)
+#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2__POR		(0x01)
+#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3		(CDC_ANA_BASE+0xDA)
+#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3__POR		(0x05)
+#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4		(CDC_ANA_BASE+0xDB)
+#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_INT_TEST1		(CDC_ANA_BASE+0xE0)
+#define MSM89XX_PMIC_ANALOG_INT_TEST1__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_INT_TEST_VAL		(CDC_ANA_BASE+0xE1)
+#define MSM89XX_PMIC_ANALOG_INT_TEST_VAL__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_TRIM_NUM		(CDC_ANA_BASE+0xF0)
+#define MSM89XX_PMIC_ANALOG_TRIM_NUM__POR		(0x04)
+#define MSM89XX_PMIC_ANALOG_TRIM_CTRL1		(CDC_ANA_BASE+0xF1)
+#define MSM89XX_PMIC_ANALOG_TRIM_CTRL1__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_TRIM_CTRL2		(CDC_ANA_BASE+0xF2)
+#define MSM89XX_PMIC_ANALOG_TRIM_CTRL2__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_TRIM_CTRL3		(CDC_ANA_BASE+0xF3)
+#define MSM89XX_PMIC_ANALOG_TRIM_CTRL3__POR		(0x00)
+#define MSM89XX_PMIC_ANALOG_TRIM_CTRL4		(CDC_ANA_BASE+0xF4)
+#define MSM89XX_PMIC_ANALOG_TRIM_CTRL4__POR		(0x00)
+
+#define MSM89XX_PMIC_CDC_NUM_REGISTERS \
+		(MSM89XX_PMIC_ANALOG_TRIM_CTRL4+1)
+#define MSM89XX_PMIC_CDC_MAX_REGISTER \
+		(MSM89XX_PMIC_CDC_NUM_REGISTERS-1)
+#define MSM89XX_PMIC_CDC_CACHE_SIZE \
+		MSM89XX_PMIC_CDC_NUM_REGISTERS
+
+
+#define MSM89XX_CDC_CORE_CLK_RX_RESET_CTL		(0x00)
+#define MSM89XX_CDC_CORE_CLK_RX_RESET_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL		(0x04)
+#define MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL		(0x08)
+#define MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CLK_RX_I2S_CTL		(0x0C)
+#define MSM89XX_CDC_CORE_CLK_RX_I2S_CTL__POR		(0x13)
+#define MSM89XX_CDC_CORE_CLK_TX_I2S_CTL		(0x10)
+#define MSM89XX_CDC_CORE_CLK_TX_I2S_CTL__POR		(0x13)
+#define MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL		(0x14)
+#define MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL		(0x18)
+#define MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CLK_OTHR_CTL		(0x1C)
+#define MSM89XX_CDC_CORE_CLK_OTHR_CTL__POR		(0x04)
+#define MSM89XX_CDC_CORE_CLK_RX_B1_CTL		(0x20)
+#define MSM89XX_CDC_CORE_CLK_RX_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CLK_MCLK_CTL		(0x24)
+#define MSM89XX_CDC_CORE_CLK_MCLK_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CLK_PDM_CTL		(0x28)
+#define MSM89XX_CDC_CORE_CLK_PDM_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CLK_SD_CTL		(0x2C)
+#define MSM89XX_CDC_CORE_CLK_SD_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CLK_WSA_VI_B1_CTL		(0x30)
+#define MSM89XX_CDC_CORE_CLK_WSA_VI_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CLK_RX_B2_CTL		(0x34)
+#define MSM89XX_CDC_CORE_CLK_RX_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX1_B1_CTL		(0x40)
+#define MSM89XX_CDC_CORE_RX1_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX2_B1_CTL		(0x60)
+#define MSM89XX_CDC_CORE_RX2_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX3_B1_CTL		(0x80)
+#define MSM89XX_CDC_CORE_RX3_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX1_B2_CTL		(0x44)
+#define MSM89XX_CDC_CORE_RX1_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX2_B2_CTL		(0x64)
+#define MSM89XX_CDC_CORE_RX2_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX3_B2_CTL		(0x84)
+#define MSM89XX_CDC_CORE_RX3_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX1_B3_CTL		(0x48)
+#define MSM89XX_CDC_CORE_RX1_B3_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX2_B3_CTL		(0x68)
+#define MSM89XX_CDC_CORE_RX2_B3_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX3_B3_CTL		(0x88)
+#define MSM89XX_CDC_CORE_RX3_B3_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX1_B4_CTL		(0x4C)
+#define MSM89XX_CDC_CORE_RX1_B4_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX2_B4_CTL		(0x6C)
+#define MSM89XX_CDC_CORE_RX2_B4_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX3_B4_CTL		(0x8C)
+#define MSM89XX_CDC_CORE_RX3_B4_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX1_B5_CTL		(0x50)
+#define MSM89XX_CDC_CORE_RX1_B5_CTL__POR		(0x68)
+#define MSM89XX_CDC_CORE_RX2_B5_CTL		(0x70)
+#define MSM89XX_CDC_CORE_RX2_B5_CTL__POR		(0x68)
+#define MSM89XX_CDC_CORE_RX3_B5_CTL		(0x90)
+#define MSM89XX_CDC_CORE_RX3_B5_CTL__POR		(0x68)
+#define MSM89XX_CDC_CORE_RX1_B6_CTL		(0x54)
+#define MSM89XX_CDC_CORE_RX1_B6_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX2_B6_CTL		(0x74)
+#define MSM89XX_CDC_CORE_RX2_B6_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX3_B6_CTL		(0x94)
+#define MSM89XX_CDC_CORE_RX3_B6_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL		(0x58)
+#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL		(0x78)
+#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL		(0x98)
+#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL		(0x5C)
+#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL		(0x7C)
+#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL		(0x9C)
+#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_TOP_GAIN_UPDATE		(0xA0)
+#define MSM89XX_CDC_CORE_TOP_GAIN_UPDATE__POR		(0x00)
+#define MSM89XX_CDC_CORE_TOP_CTL		(0xA4)
+#define MSM89XX_CDC_CORE_TOP_CTL__POR			(0x01)
+#define MSM89XX_CDC_CORE_COMP0_B1_CTL		(0xB0)
+#define MSM89XX_CDC_CORE_COMP0_B1_CTL__POR		(0x30)
+#define MSM89XX_CDC_CORE_COMP0_B2_CTL		(0xB4)
+#define MSM89XX_CDC_CORE_COMP0_B2_CTL__POR		(0xB5)
+#define MSM89XX_CDC_CORE_COMP0_B3_CTL		(0xB8)
+#define MSM89XX_CDC_CORE_COMP0_B3_CTL__POR		(0x28)
+#define MSM89XX_CDC_CORE_COMP0_B4_CTL		(0xBC)
+#define MSM89XX_CDC_CORE_COMP0_B4_CTL__POR		(0x37)
+#define MSM89XX_CDC_CORE_COMP0_B5_CTL		(0xC0)
+#define MSM89XX_CDC_CORE_COMP0_B5_CTL__POR		(0x7F)
+#define MSM89XX_CDC_CORE_COMP0_B6_CTL		(0xC4)
+#define MSM89XX_CDC_CORE_COMP0_B6_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS		(0xC8)
+#define MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS__POR		(0x03)
+#define MSM89XX_CDC_CORE_COMP0_FS_CFG		(0xCC)
+#define MSM89XX_CDC_CORE_COMP0_FS_CFG__POR		(0x03)
+#define MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL		(0xD0)
+#define MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL__POR		(0x02)
+#define MSM89XX_CDC_CORE_DEBUG_DESER1_CTL		(0xE0)
+#define MSM89XX_CDC_CORE_DEBUG_DESER1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_DEBUG_DESER2_CTL		(0xE4)
+#define MSM89XX_CDC_CORE_DEBUG_DESER2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG		(0xE8)
+#define MSM89XX_CDC_CORE_DEBUG_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG		(0xEC)
+#define MSM89XX_CDC_CORE_DEBUG_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG		(0xF0)
+#define MSM89XX_CDC_CORE_DEBUG_B3_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL		(0x100)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL		(0x140)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL		(0x104)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL		(0x144)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL		(0x108)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL		(0x148)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL		(0x10C)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL		(0x14C)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL		(0x110)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL		(0x150)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL		(0x114)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL		(0x154)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL		(0x118)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL		(0x158)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL		(0x11C)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL		(0x15C)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR1_CTL		(0x120)
+#define MSM89XX_CDC_CORE_IIR1_CTL__POR		(0x40)
+#define MSM89XX_CDC_CORE_IIR2_CTL		(0x160)
+#define MSM89XX_CDC_CORE_IIR2_CTL__POR		(0x40)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL		(0x124)
+#define MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL		(0x164)
+#define MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL		(0x128)
+#define MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL		(0x168)
+#define MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL		(0x12C)
+#define MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL		(0x16C)
+#define MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_RX1_B1_CTL		(0x180)
+#define MSM89XX_CDC_CORE_CONN_RX1_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_RX1_B2_CTL		(0x184)
+#define MSM89XX_CDC_CORE_CONN_RX1_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_RX1_B3_CTL		(0x188)
+#define MSM89XX_CDC_CORE_CONN_RX1_B3_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_RX2_B1_CTL		(0x18C)
+#define MSM89XX_CDC_CORE_CONN_RX2_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_RX2_B2_CTL		(0x190)
+#define MSM89XX_CDC_CORE_CONN_RX2_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_RX2_B3_CTL		(0x194)
+#define MSM89XX_CDC_CORE_CONN_RX2_B3_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_RX3_B1_CTL		(0x198)
+#define MSM89XX_CDC_CORE_CONN_RX3_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_RX3_B2_CTL		(0x19C)
+#define MSM89XX_CDC_CORE_CONN_RX3_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_TX_B1_CTL		(0x1A0)
+#define MSM89XX_CDC_CORE_CONN_TX_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL		(0x1A8)
+#define MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL		(0x1AC)
+#define MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL		(0x1B0)
+#define MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL		(0x1B4)
+#define MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL		(0x1B8)
+#define MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL		(0x1BC)
+#define MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL		(0x1C0)
+#define MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL		(0x1C4)
+#define MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL		(0x1C8)
+#define MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER		(0x280)
+#define MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER		(0x2A0)
+#define MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER		(0x2C0)
+#define MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER		(0x2E0)
+#define MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN		(0x284)
+#define MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN		(0x2A4)
+#define MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN		(0x2C4)
+#define MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN		(0x2E4)
+#define MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG		(0x288)
+#define MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG		(0x2A8)
+#define MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG		(0x2C8)
+#define MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG		(0x2E8)
+#define MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX1_MUX_CTL		(0x28C)
+#define MSM89XX_CDC_CORE_TX1_MUX_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX2_MUX_CTL		(0x2AC)
+#define MSM89XX_CDC_CORE_TX2_MUX_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX3_MUX_CTL		(0x2CC)
+#define MSM89XX_CDC_CORE_TX3_MUX_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX4_MUX_CTL		(0x2EC)
+#define MSM89XX_CDC_CORE_TX4_MUX_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX1_CLK_FS_CTL		(0x290)
+#define MSM89XX_CDC_CORE_TX1_CLK_FS_CTL__POR		(0x03)
+#define MSM89XX_CDC_CORE_TX2_CLK_FS_CTL		(0x2B0)
+#define MSM89XX_CDC_CORE_TX2_CLK_FS_CTL__POR		(0x03)
+#define MSM89XX_CDC_CORE_TX3_CLK_FS_CTL		(0x2D0)
+#define MSM89XX_CDC_CORE_TX3_CLK_FS_CTL__POR		(0x03)
+#define MSM89XX_CDC_CORE_TX4_CLK_FS_CTL		(0x2F0)
+#define MSM89XX_CDC_CORE_TX4_CLK_FS_CTL__POR		(0x03)
+#define MSM89XX_CDC_CORE_TX1_DMIC_CTL		(0x294)
+#define MSM89XX_CDC_CORE_TX1_DMIC_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX2_DMIC_CTL		(0x2B4)
+#define MSM89XX_CDC_CORE_TX2_DMIC_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX3_DMIC_CTL		(0x2D4)
+#define MSM89XX_CDC_CORE_TX3_DMIC_CTL__POR		(0x00)
+#define MSM89XX_CDC_CORE_TX4_DMIC_CTL		(0x2F4)
+#define MSM89XX_CDC_CORE_TX4_DMIC_CTL__POR		(0x00)
+
+#define MSM89XX_CDC_CORE_NUM_REGISTERS \
+		(MSM89XX_CDC_CORE_TX4_DMIC_CTL+1)
+#define MSM89XX_CDC_CORE_MAX_REGISTER \
+		(MSM89XX_CDC_CORE_NUM_REGISTERS-1)
+#define MSM89XX_CDC_CORE_CACHE_SIZE \
+		MSM89XX_CDC_CORE_NUM_REGISTERS
+#endif