powerpc/83xx: refactor mpc8360e quirk for kmeter1
Move the code for this quirk to a dedicated function. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Gerlando Falauto
Kumar Gala
parent
89491d83b2
commit
14f40f31e8
1 changed files with 77 additions and 72 deletions
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@ -43,6 +43,82 @@
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#include "mpc83xx.h"
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#include "mpc83xx.h"
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#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
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#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
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static void quirk_mpc8360e_qe_enet10(void)
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{
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/*
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* handle mpc8360E Erratum QE_ENET10:
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* RGMII AC values do not meet the specification
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*/
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uint svid = mfspr(SPRN_SVR);
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struct device_node *np_par;
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struct resource res;
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void __iomem *base;
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int ret;
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np_par = of_find_node_by_name(NULL, "par_io");
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if (np_par == NULL) {
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pr_warn("%s couldn;t find par_io node\n", __func__);
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return;
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}
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/* Map Parallel I/O ports registers */
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ret = of_address_to_resource(np_par, 0, &res);
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if (ret) {
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pr_warn("%s couldn;t map par_io registers\n", __func__);
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return;
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}
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base = ioremap(res.start, res.end - res.start + 1);
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/*
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* set output delay adjustments to default values according
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* table 5 in Errata Rev. 5, 9/2011:
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*
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* write 0b01 to UCC1 bits 18:19
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* write 0b01 to UCC2 option 1 bits 4:5
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* write 0b01 to UCC2 option 2 bits 16:17
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*/
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clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
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/*
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* set output delay adjustments to default values according
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* table 3-13 in Reference Manual Rev.3 05/2010:
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*
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* write 0b01 to UCC2 option 2 bits 16:17
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* write 0b0101 to UCC1 bits 20:23
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* write 0b0101 to UCC2 option 1 bits 24:27
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*/
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clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
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if (SVR_REV(svid) == 0x0021) {
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/*
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* UCC2 option 1: write 0b1010 to bits 24:27
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* at address IMMRBAR+0x14AC
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*/
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clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
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} else if (SVR_REV(svid) == 0x0020) {
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/*
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* UCC1: write 0b11 to bits 18:19
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* at address IMMRBAR+0x14A8
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*/
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setbits32((base + 0xa8), 0x00003000);
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/*
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* UCC2 option 1: write 0b11 to bits 4:5
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* at address IMMRBAR+0x14A8
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*/
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setbits32((base + 0xa8), 0x0c000000);
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/*
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* UCC2 option 2: write 0b11 to bits 16:17
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* at address IMMRBAR+0x14AC
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*/
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setbits32((base + 0xac), 0x0000c000);
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}
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iounmap(base);
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of_node_put(np_par);
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}
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/* ************************************************************************
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/* ************************************************************************
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*
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*
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* Setup the architecture
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* Setup the architecture
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@ -73,80 +149,9 @@ static void __init mpc83xx_km_setup_arch(void)
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for_each_node_by_name(np, "ucc")
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for_each_node_by_name(np, "ucc")
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par_io_of_config(np);
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par_io_of_config(np);
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}
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}
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np = of_find_compatible_node(NULL, "network", "ucc_geth");
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np = of_find_compatible_node(NULL, "network", "ucc_geth");
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if (np != NULL) {
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if (np != NULL) {
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/*
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quirk_mpc8360e_qe_enet10();
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* handle mpc8360E Erratum QE_ENET10:
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* RGMII AC values do not meet the specification
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*/
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uint svid = mfspr(SPRN_SVR);
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struct device_node *np_par;
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struct resource res;
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void __iomem *base;
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int ret;
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np_par = of_find_node_by_name(NULL, "par_io");
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if (np_par == NULL) {
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pr_warn("%s couldn;t find par_io node\n", __func__);
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return;
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}
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/* Map Parallel I/O ports registers */
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ret = of_address_to_resource(np_par, 0, &res);
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if (ret) {
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pr_warn("%s couldn;t map par_io registers\n", __func__);
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return;
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}
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base = ioremap(res.start, res.end - res.start + 1);
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/*
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* set output delay adjustments to default values according
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* table 5 in Errata Rev. 5, 9/2011:
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*
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* write 0b01 to UCC1 bits 18:19
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* write 0b01 to UCC2 option 1 bits 4:5
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* write 0b01 to UCC2 option 2 bits 16:17
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*/
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clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
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/*
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* set output delay adjustments to default values according
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* table 3-13 in Reference Manual Rev.3 05/2010:
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*
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* write 0b01 to UCC2 option 2 bits 16:17
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* write 0b0101 to UCC1 bits 20:23
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* write 0b0101 to UCC2 option 1 bits 24:27
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*/
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clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
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if (SVR_REV(svid) == 0x0021) {
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/*
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* UCC2 option 1: write 0b1010 to bits 24:27
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* at address IMMRBAR+0x14AC
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*/
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clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
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} else if (SVR_REV(svid) == 0x0020) {
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/*
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* UCC1: write 0b11 to bits 18:19
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* at address IMMRBAR+0x14A8
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*/
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setbits32((base + 0xa8), 0x00003000);
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/*
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* UCC2 option 1: write 0b11 to bits 4:5
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* at address IMMRBAR+0x14A8
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*/
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setbits32((base + 0xa8), 0x0c000000);
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/*
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* UCC2 option 2: write 0b11 to bits 16:17
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* at address IMMRBAR+0x14AC
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*/
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setbits32((base + 0xac), 0x0000c000);
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}
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iounmap(base);
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of_node_put(np_par);
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of_node_put(np);
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of_node_put(np);
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}
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}
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#endif /* CONFIG_QUICC_ENGINE */
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#endif /* CONFIG_QUICC_ENGINE */
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