clk: qcom: Add support for debugfs measure clock
Introduce clk_debug_mux which would support clocks to be allowed to measure clock frequency from debugfs. Change-Id: I81c32a876b33f5a7773485a76897ff9cbed45a76 Signed-off-by: Taniya Das <tdas@codeaurora.org>
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368fecd7df
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151d532101
5 changed files with 317 additions and 1 deletions
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@ -2801,6 +2801,8 @@ static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
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goto err_out;
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}
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clk_debug_measure_add(core->hw, core->dentry);
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ret = 0;
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goto out;
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@ -2930,8 +2932,10 @@ static int __init clk_debug_init(void)
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return -ENOMEM;
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mutex_lock(&clk_debug_lock);
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hlist_for_each_entry(core, &clk_debug_list, debug_node)
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hlist_for_each_entry(core, &clk_debug_list, debug_node) {
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clk_register_debug(core->hw, core->dentry);
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clk_debug_create_one(core, rootdir);
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}
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inited = 1;
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mutex_unlock(&clk_debug_lock);
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@ -23,6 +23,8 @@ void __clk_free_clk(struct clk *clk);
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/* Debugfs API to print the enabled clocks */
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void clock_debug_print_enabled(void);
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int clk_register_debug(struct clk_hw *hw, struct dentry *dentry);
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void clk_debug_measure_add(struct clk_hw *hw, struct dentry *dentry);
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#else
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/* All these casts to avoid ifdefs in clkdev... */
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@ -11,6 +11,7 @@
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/export.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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@ -286,4 +287,221 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
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}
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EXPORT_SYMBOL_GPL(qcom_cc_probe);
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/* Debugfs Support */
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static struct clk_hw *measure;
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DEFINE_SPINLOCK(clk_reg_lock);
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/* Sample clock for 'ticks' reference clock ticks. */
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static u32 run_measurement(unsigned ticks, struct regmap *regmap,
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u32 ctl_reg, u32 status_reg)
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{
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u32 regval;
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/* Stop counters and set the XO4 counter start value. */
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regmap_write(regmap, ctl_reg, ticks);
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regmap_read(regmap, status_reg, ®val);
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/* Wait for timer to become ready. */
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while ((regval & BIT(25)) != 0) {
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cpu_relax();
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regmap_read(regmap, status_reg, ®val);
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}
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/* Run measurement and wait for completion. */
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regmap_write(regmap, ctl_reg, (BIT(20)|ticks));
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regmap_read(regmap, ctl_reg, ®val);
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regmap_read(regmap, status_reg, ®val);
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while ((regval & BIT(25)) == 0) {
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cpu_relax();
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regmap_read(regmap, status_reg, ®val);
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}
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/* Return measured ticks. */
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regmap_read(regmap, status_reg, ®val);
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regval &= BM(24, 0);
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return regval;
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}
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/*
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* Perform a hardware rate measurement for a given clock.
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* FOR DEBUG USE ONLY: Measurements take ~15 ms!
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*/
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static unsigned long clk_debug_mux_measure_rate(struct clk_hw *hw)
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{
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unsigned long flags, ret = 0;
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u32 gcc_xo4_reg, sample_ticks = 0x10000, multiplier = 1;
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u64 raw_count_short, raw_count_full;
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struct clk_debug_mux *meas = to_clk_measure(hw);
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struct measure_clk_data *data = meas->priv;
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spin_lock_irqsave(&clk_reg_lock, flags);
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clk_prepare_enable(data->cxo);
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/* Enable CXO/4 and RINGOSC branch. */
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regmap_read(meas->regmap[GCC], data->xo_div4_cbcr, &gcc_xo4_reg);
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gcc_xo4_reg |= BIT(0);
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regmap_write(meas->regmap[GCC], data->xo_div4_cbcr, gcc_xo4_reg);
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/*
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* The ring oscillator counter will not reset if the measured clock
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* is not running. To detect this, run a short measurement before
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* the full measurement. If the raw results of the two are the same
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* then the clock must be off.
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*/
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/* Run a short measurement. (~1 ms) */
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raw_count_short = run_measurement(0x1000, meas->regmap[GCC],
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data->ctl_reg, data->status_reg);
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/* Run a full measurement. (~14 ms) */
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raw_count_full = run_measurement(sample_ticks, meas->regmap[GCC],
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data->ctl_reg, data->status_reg);
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gcc_xo4_reg &= ~BIT(0);
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regmap_write(meas->regmap[GCC], data->xo_div4_cbcr, gcc_xo4_reg);
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/* Return 0 if the clock is off. */
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if (raw_count_full == raw_count_short)
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ret = 0;
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else {
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/* Compute rate in Hz. */
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raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
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do_div(raw_count_full, ((sample_ticks * 10) + 35));
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ret = (raw_count_full * multiplier);
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}
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clk_disable_unprepare(data->cxo);
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spin_unlock_irqrestore(&clk_reg_lock, flags);
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return ret;
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}
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static u8 clk_debug_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_debug_mux *meas = to_clk_measure(hw);
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int i, num_parents = clk_hw_get_num_parents(hw);
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for (i = 0; i < num_parents; i++) {
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if (!strcmp(meas->parent[i].parents,
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hw->init->parent_names[i])) {
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pr_debug("%s :Clock name %s index %d\n", __func__,
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hw->init->name, i);
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return i;
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}
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}
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return 0;
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}
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static int clk_debug_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_debug_mux *meas = to_clk_measure(hw);
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u32 regval = 0;
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int dbg_cc = 0;
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dbg_cc = meas->parent[index].dbg_cc;
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if (dbg_cc != GCC) {
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regmap_read(meas->regmap[dbg_cc], 0x0, ®val);
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if (meas->parent[index].mask)
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regval &= ~meas->parent[index].mask <<
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meas->parent[index].shift;
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else
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regval &= ~meas->mask;
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regval |= (meas->parent[index].next_sel & meas->mask);
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if (meas->parent[index].en_mask == 0xFF)
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/* Skip en_mask */
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regval = regval;
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else if (meas->parent[index].en_mask)
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regval |= meas->parent[index].en_mask;
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else
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regval |= meas->en_mask;
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regmap_write(meas->regmap[dbg_cc], 0x0, regval);
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}
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/* update the debug sel for GCC */
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regmap_read(meas->regmap[GCC], meas->debug_offset, ®val);
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/* clear post divider bits */
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regval &= ~BM(15, 12);
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regval &= ~meas->mask;
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regval |= (meas->parent[index].sel & meas->mask);
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regval |= meas->en_mask;
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regmap_write(meas->regmap[GCC], meas->debug_offset, regval);
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return 0;
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}
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const struct clk_ops clk_debug_mux_ops = {
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.get_parent = clk_debug_mux_get_parent,
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.set_parent = clk_debug_mux_set_parent,
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};
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EXPORT_SYMBOL_GPL(clk_debug_mux_ops);
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static int clk_debug_measure_get(void *data, u64 *val)
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{
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struct clk_hw *hw = data, *par;
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int ret = 0;
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unsigned long meas_rate, sw_rate;
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ret = clk_set_parent(measure->clk, hw->clk);
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if (!ret) {
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par = measure;
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while (par && par != hw) {
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if (par->init->ops->enable)
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par->init->ops->enable(par);
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par = clk_hw_get_parent(par);
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}
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*val = clk_debug_mux_measure_rate(measure);
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}
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meas_rate = clk_get_rate(hw->clk);
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sw_rate = clk_get_rate(clk_hw_get_parent(measure)->clk);
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if (sw_rate && meas_rate >= (sw_rate * 2))
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*val *= DIV_ROUND_CLOSEST(meas_rate, sw_rate);
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return ret;
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}
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DEFINE_SIMPLE_ATTRIBUTE(clk_measure_fops, clk_debug_measure_get,
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NULL, "%lld\n");
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void clk_debug_measure_add(struct clk_hw *hw, struct dentry *dentry)
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{
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if (IS_ERR_OR_NULL(measure))
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return;
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if (clk_set_parent(measure->clk, hw->clk))
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return;
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debugfs_create_file("measure", S_IRUGO, dentry, hw,
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&clk_measure_fops);
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}
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EXPORT_SYMBOL_GPL(clk_debug_measure_add);
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int clk_register_debug(struct clk_hw *hw, struct dentry *dentry)
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{
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if (IS_ERR_OR_NULL(measure)) {
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if (hw->init->flags & CLK_IS_MEASURE)
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measure = hw;
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if (!IS_ERR_OR_NULL(measure))
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clk_debug_measure_add(hw, dentry);
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(clk_register_debug);
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MODULE_LICENSE("GPL v2");
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@ -51,4 +51,95 @@ extern int qcom_cc_really_probe(struct platform_device *pdev,
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extern int qcom_cc_probe(struct platform_device *pdev,
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const struct qcom_cc_desc *desc);
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extern struct clk_ops clk_dummy_ops;
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/* Debugfs Measure Clocks */
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/**
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* struct measure_clk_data - Structure of clk measure
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*
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* @cxo: XO clock.
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* @xo_div4_cbcr: offset of debug XO/4 div register.
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* @ctl_reg: offset of debug control register.
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* @status_reg: offset of debug status register.
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*
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*/
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struct measure_clk_data {
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struct clk *cxo;
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u32 xo_div4_cbcr;
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u32 ctl_reg;
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u32 status_reg;
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};
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/**
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* List of Debug clock controllers.
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*/
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enum debug_cc {
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GCC,
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MMCC,
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GPU,
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CPU,
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};
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/**
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* struct clk_src - Struture of clock source for debug mux
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*
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* @parents: clock name to be used as parent for debug mux.
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* @sel: debug mux index at global clock controller.
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* @dbg_cc: indicates the clock controller for recursive debug clock
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* controllers.
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* @next_sel: indicates the debug mux index at recursive debug mux.
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* @mask: indicates the mask required at recursive debug mux.
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* @shift: indicates the shift required at recursive debug mux.
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* @en_mask: indicates the enable bit mask at recursive debug mux.
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* Incase the recursive debug mux does not have a enable bit,
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* 0xFF should be used to indicate the same, otherwise global
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* enable bit would be used.
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*/
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struct clk_src {
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const char *parents;
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int sel;
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enum debug_cc dbg_cc;
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int next_sel;
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u32 mask;
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u32 shift;
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u32 en_mask;
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};
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#define MUX_SRC_LIST(...) \
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.parent = (struct clk_src[]){__VA_ARGS__}, \
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.num_parents = ARRAY_SIZE(((struct clk_src[]){__VA_ARGS__}))
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/**
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* struct clk_debug_mux - Struture of clock debug mux
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*
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* @parent: structure of clk_src
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* @num_parents: number of parents
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* @regmap: regmaps of debug mux
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* @num_parent_regmap: number of regmap of debug mux
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* @priv: private measure_clk_data to be used by debug mux
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* @en_mask: indicates the enable bit mask at global clock
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* controller debug mux.
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* @mask: indicates the mask to be used at global clock
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* controller debug mux.
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* @debug_offset: Start of debug mux offset.
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* @hw: handle between common and hardware-specific interfaces.
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*/
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struct clk_debug_mux {
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struct clk_src *parent;
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int num_parents;
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struct regmap **regmap;
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int num_parent_regmap;
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void *priv;
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u32 en_mask;
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u32 mask;
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u32 debug_offset;
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struct clk_hw hw;
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};
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#define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
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#define to_clk_measure(_hw) container_of((_hw), struct clk_debug_mux, hw)
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extern const struct clk_ops clk_debug_mux_ops;
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#endif
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@ -33,6 +33,7 @@
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#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
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#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
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#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
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#define CLK_IS_MEASURE BIT(14) /* measure clock */
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struct clk;
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struct clk_hw;
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