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staging: rtl8192e: Rename rtl8192_setBBreg

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Use naming schema found in other rtlwifi devices.
Rename rtl8192_setBBreg to rtl92e_set_bb_reg.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mateusz Kulikowski 2015-07-19 19:27:57 +02:00 • committed by Greg Kroah-Hartman
parent 3c351feca9
commit 153f9ddbe9
5 changed files with 182 additions and 186 deletions
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24
drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c
View file

@ -115,14 +115,14 @@ static bool phy_RF8256_Config_ParaFile(struct net_device *dev)
break; break;
} }
rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); rtl92e_set_bb_reg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); rtl92e_set_bb_reg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
b3WireAddressLength, 0x0); b3WireAddressLength, 0x0);
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
b3WireDataLength, 0x0); b3WireDataLength, 0x0);
rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 0x0, rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 0x0,
bMask12Bits, 0xbf); bMask12Bits, 0xbf);
@ -206,13 +206,13 @@ static bool phy_RF8256_Config_ParaFile(struct net_device *dev)
switch (eRFPath) { switch (eRFPath) {
case RF90_PATH_A: case RF90_PATH_A:
case RF90_PATH_C: case RF90_PATH_C:
rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, rtl92e_set_bb_reg(dev, pPhyReg->rfintfs, bRFSI_RFENV,
u4RegValue); u4RegValue);
break; break;
case RF90_PATH_B: case RF90_PATH_B:
case RF90_PATH_D: case RF90_PATH_D:
rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, rtl92e_set_bb_reg(dev, pPhyReg->rfintfs,
u4RegValue); bRFSI_RFENV<<16, u4RegValue);
break; break;
} }
@ -254,7 +254,7 @@ void rtl92e_set_cck_tx_power(struct net_device *dev, u8 powerlevel)
} }
if (TxAGC > 0x24) if (TxAGC > 0x24)
TxAGC = 0x24; TxAGC = 0x24;
rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); rtl92e_set_bb_reg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
} }
@ -300,7 +300,7 @@ void rtl92e_set_ofdm_tx_power(struct net_device *dev, u8 powerlevel)
else else
writeVal = (byte3 << 24) | (byte2 << 16) | writeVal = (byte3 << 24) | (byte2 << 16) |
(byte1 << 8) | byte0; (byte1 << 8) | byte0;
rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); rtl92e_set_bb_reg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
} }
} }

4
drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c
View file

@ -872,8 +872,8 @@ start:
} }
rtl8192_phy_updateInitGain(dev); rtl8192_phy_updateInitGain(dev);
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
write_nic_byte(dev, 0x87, 0x0); write_nic_byte(dev, 0x87, 0x0);

165
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c
View file

@ -80,8 +80,8 @@ u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath)
return ret; return ret;
} }
void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
u32 dwData) u32 dwData)
{ {
u32 OriginalValue, BitShift, NewValue; u32 OriginalValue, BitShift, NewValue;
@ -117,19 +117,19 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
Offset &= 0x3f; Offset &= 0x3f;
if (priv->rf_chip == RF_8256) { if (priv->rf_chip == RF_8256) {
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
if (Offset >= 31) { if (Offset >= 31) {
priv->RfReg0Value[eRFPath] |= 0x140; priv->RfReg0Value[eRFPath] |= 0x140;
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord, bMaskDWord,
(priv->RfReg0Value[eRFPath]<<16)); (priv->RfReg0Value[eRFPath]<<16));
NewOffset = Offset - 30; NewOffset = Offset - 30;
} else if (Offset >= 16) { } else if (Offset >= 16) {
priv->RfReg0Value[eRFPath] |= 0x100; priv->RfReg0Value[eRFPath] |= 0x100;
priv->RfReg0Value[eRFPath] &= (~0x40); priv->RfReg0Value[eRFPath] &= (~0x40);
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord, bMaskDWord,
(priv->RfReg0Value[eRFPath]<<16)); (priv->RfReg0Value[eRFPath]<<16));
NewOffset = Offset - 15; NewOffset = Offset - 15;
} else } else
@ -139,10 +139,10 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
"check RF type here, need to be 8256\n"); "check RF type here, need to be 8256\n");
NewOffset = Offset; NewOffset = Offset;
} }
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
NewOffset); NewOffset);
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
mdelay(1); mdelay(1);
@ -152,10 +152,10 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
if (priv->rf_chip == RF_8256) { if (priv->rf_chip == RF_8256) {
priv->RfReg0Value[eRFPath] &= 0xebf; priv->RfReg0Value[eRFPath] &= 0xebf;
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
(priv->RfReg0Value[eRFPath] << 16)); (priv->RfReg0Value[eRFPath] << 16));
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
} }
@ -173,20 +173,20 @@ static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
Offset &= 0x3f; Offset &= 0x3f;
if (priv->rf_chip == RF_8256) { if (priv->rf_chip == RF_8256) {
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
if (Offset >= 31) { if (Offset >= 31) {
priv->RfReg0Value[eRFPath] |= 0x140; priv->RfReg0Value[eRFPath] |= 0x140;
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord, bMaskDWord,
(priv->RfReg0Value[eRFPath] << 16)); (priv->RfReg0Value[eRFPath] << 16));
NewOffset = Offset - 30; NewOffset = Offset - 30;
} else if (Offset >= 16) { } else if (Offset >= 16) {
priv->RfReg0Value[eRFPath] |= 0x100; priv->RfReg0Value[eRFPath] |= 0x100;
priv->RfReg0Value[eRFPath] &= (~0x40); priv->RfReg0Value[eRFPath] &= (~0x40);
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
bMaskDWord, bMaskDWord,
(priv->RfReg0Value[eRFPath] << 16)); (priv->RfReg0Value[eRFPath] << 16));
NewOffset = Offset - 15; NewOffset = Offset - 15;
} else } else
NewOffset = Offset; NewOffset = Offset;
@ -198,7 +198,7 @@ static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
DataAndAddr = (Data<<16) | (NewOffset&0x3f); DataAndAddr = (Data<<16) | (NewOffset&0x3f);
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
if (Offset == 0x0) if (Offset == 0x0)
priv->RfReg0Value[eRFPath] = Data; priv->RfReg0Value[eRFPath] = Data;
@ -206,13 +206,11 @@ static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
if (priv->rf_chip == RF_8256) { if (priv->rf_chip == RF_8256) {
if (Offset != 0) { if (Offset != 0) {
priv->RfReg0Value[eRFPath] &= 0xebf; priv->RfReg0Value[eRFPath] &= 0xebf;
rtl8192_setBBreg( rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
dev, bMaskDWord,
pPhyReg->rf3wireOffset, (priv->RfReg0Value[eRFPath] << 16));
bMaskDWord,
(priv->RfReg0Value[eRFPath] << 16));
} }
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
} }
} }
@ -350,8 +348,8 @@ void rtl92e_config_mac(struct net_device *dev)
pdwArray[i], pdwArray[i+1], pdwArray[i+2]); pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
if (pdwArray[i] == 0x318) if (pdwArray[i] == 0x318)
pdwArray[i+2] = 0x00000800; pdwArray[i+2] = 0x00000800;
rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], rtl92e_set_bb_reg(dev, pdwArray[i], pdwArray[i+1],
pdwArray[i+2]); pdwArray[i+2]);
} }
return; return;
@ -377,9 +375,9 @@ static void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
if (ConfigType == BaseBand_Config_PHY_REG) { if (ConfigType == BaseBand_Config_PHY_REG) {
for (i = 0; i < PHY_REGArrayLen; i += 2) { for (i = 0; i < PHY_REGArrayLen; i += 2) {
rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], rtl92e_set_bb_reg(dev, Rtl819XPHY_REGArray_Table[i],
bMaskDWord, bMaskDWord,
Rtl819XPHY_REGArray_Table[i+1]); Rtl819XPHY_REGArray_Table[i+1]);
RT_TRACE(COMP_DBG, RT_TRACE(COMP_DBG,
"i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n", "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
i, Rtl819XPHY_REGArray_Table[i], i, Rtl819XPHY_REGArray_Table[i],
@ -387,9 +385,9 @@ static void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
} }
} else if (ConfigType == BaseBand_Config_AGC_TAB) { } else if (ConfigType == BaseBand_Config_AGC_TAB) {
for (i = 0; i < AGCTAB_ArrayLen; i += 2) { for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], rtl92e_set_bb_reg(dev, Rtl819XAGCTAB_Array_Table[i],
bMaskDWord, bMaskDWord,
Rtl819XAGCTAB_Array_Table[i+1]); Rtl819XAGCTAB_Array_Table[i+1]);
RT_TRACE(COMP_DBG, RT_TRACE(COMP_DBG,
"i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n", "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",
i, Rtl819XAGCTAB_Array_Table[i], i, Rtl819XAGCTAB_Array_Table[i],
@ -572,7 +570,7 @@ static bool rtl8192_BB_Config_ParaFile(struct net_device *dev)
return rtStatus; return rtStatus;
} }
} }
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
dwRegValue = read_nic_dword(dev, CPU_GEN); dwRegValue = read_nic_dword(dev, CPU_GEN);
@ -587,13 +585,13 @@ static bool rtl8192_BB_Config_ParaFile(struct net_device *dev)
priv->AntennaTxPwDiff[0]); priv->AntennaTxPwDiff[0]);
else else
dwRegValue = 0x0; dwRegValue = 0x0;
rtl8192_setBBreg(dev, rFPGA0_TxGainStage, rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
(bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
dwRegValue = priv->CrystalCap; dwRegValue = priv->CrystalCap;
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
dwRegValue); dwRegValue);
} }
return rtStatus; return rtStatus;
@ -670,8 +668,9 @@ void rtl92e_set_tx_power(struct net_device *dev, u8 channel)
priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[1]<<4 |
priv->AntennaTxPwDiff[0]); priv->AntennaTxPwDiff[0]);
rtl8192_setBBreg(dev, rFPGA0_TxGainStage, rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
(bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); (bXBTxAGC|bXCTxAGC|bXDTxAGC),
u4RegValue);
} }
} }
switch (priv->rf_chip) { switch (priv->rf_chip) {
@ -1199,8 +1198,8 @@ static void rtl8192_SetBWModeWorkItem(struct net_device *dev)
switch (priv->CurrentChannelBW) { switch (priv->CurrentChannelBW) {
case HT_CHANNEL_WIDTH_20: case HT_CHANNEL_WIDTH_20:
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
if (!priv->btxpower_tracking) { if (!priv->btxpower_tracking) {
write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
@ -1210,12 +1209,12 @@ static void rtl8192_SetBWModeWorkItem(struct net_device *dev)
CCK_Tx_Power_Track_BW_Switch(dev); CCK_Tx_Power_Track_BW_Switch(dev);
} }
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
break; break;
case HT_CHANNEL_WIDTH_20_40: case HT_CHANNEL_WIDTH_20_40:
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
if (!priv->btxpower_tracking) { if (!priv->btxpower_tracking) {
write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
@ -1225,12 +1224,12 @@ static void rtl8192_SetBWModeWorkItem(struct net_device *dev)
CCK_Tx_Power_Track_BW_Switch(dev); CCK_Tx_Power_Track_BW_Switch(dev);
} }
rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand,
(priv->nCur40MhzPrimeSC>>1)); (priv->nCur40MhzPrimeSC>>1));
rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00,
priv->nCur40MhzPrimeSC); priv->nCur40MhzPrimeSC);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
break; break;
default: default:
netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__,
@ -1307,7 +1306,7 @@ void rtl92e_init_gain(struct net_device *dev, u8 Operation)
BitMask = bMaskByte0; BitMask = bMaskByte0;
if (dm_digtable.dig_algorithm == if (dm_digtable.dig_algorithm ==
DIG_ALGO_BY_FALSE_ALARM) DIG_ALGO_BY_FALSE_ALARM)
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
priv->initgain_backup.xaagccore1 = priv->initgain_backup.xaagccore1 =
(u8)rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1, (u8)rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1,
BitMask); BitMask);
@ -1356,18 +1355,18 @@ void rtl92e_init_gain(struct net_device *dev, u8 Operation)
BitMask = 0x7f; BitMask = 0x7f;
if (dm_digtable.dig_algorithm == if (dm_digtable.dig_algorithm ==
DIG_ALGO_BY_FALSE_ALARM) DIG_ALGO_BY_FALSE_ALARM)
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask,
(u32)priv->initgain_backup.xaagccore1); (u32)priv->initgain_backup.xaagccore1);
rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask,
(u32)priv->initgain_backup.xbagccore1); (u32)priv->initgain_backup.xbagccore1);
rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask,
(u32)priv->initgain_backup.xcagccore1); (u32)priv->initgain_backup.xcagccore1);
rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask,
(u32)priv->initgain_backup.xdagccore1); (u32)priv->initgain_backup.xdagccore1);
BitMask = bMaskByte2; BitMask = bMaskByte2;
rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, rtl92e_set_bb_reg(dev, rCCK0_CCA, BitMask,
(u32)priv->initgain_backup.cca); (u32)priv->initgain_backup.cca);
RT_TRACE(COMP_SCAN, RT_TRACE(COMP_SCAN,
@ -1391,7 +1390,7 @@ void rtl92e_init_gain(struct net_device *dev, u8 Operation)
if (dm_digtable.dig_algorithm == if (dm_digtable.dig_algorithm ==
DIG_ALGO_BY_FALSE_ALARM) DIG_ALGO_BY_FALSE_ALARM)
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1);
break; break;
default: default:
RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
@ -1403,13 +1402,13 @@ void rtl92e_init_gain(struct net_device *dev, u8 Operation)
void rtl92e_set_rf_off(struct net_device *dev) void rtl92e_set_rf_off(struct net_device *dev)
{ {
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07); write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07);
} }
@ -1458,22 +1457,22 @@ static bool SetRFPowerState8190(struct net_device *dev,
} else { } else {
write_nic_byte(dev, ANAPAR, 0x37); write_nic_byte(dev, ANAPAR, 0x37);
mdelay(1); mdelay(1);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
0x4, 0x1); 0x4, 0x1);
priv->bHwRfOffAction = 0; priv->bHwRfOffAction = 0;
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE,
BIT4, 0x1); BIT4, 0x1);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4,
0x300, 0x3); 0x300, 0x3);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
0x18, 0x3); 0x18, 0x3);
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable,
0x3); 0x3, 0x3);
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable,
0x3); 0x3, 0x3);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
0x60, 0x3); 0x60, 0x3);
} }

4
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h
View file

@ -68,8 +68,8 @@ enum rf90_radio_path {
#define bMaskDWord 0xffffffff #define bMaskDWord 0xffffffff
extern u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath); extern u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath);
extern void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, extern void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr,
u32 dwBitMask, u32 dwData); u32 dwBitMask, u32 dwData);
extern u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, extern u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr,
u32 dwBitMask); u32 dwBitMask);
extern void rtl92e_set_rf_reg(struct net_device *dev, extern void rtl92e_set_rf_reg(struct net_device *dev,

171
drivers/staging/rtl8192e/rtl8192e/rtl_dm.c
View file

@ -561,40 +561,40 @@ static void dm_tx_update_tssi_weak_signal(struct net_device *dev, u8 RF_Type)
p->rfa_txpowertrackingindex--; p->rfa_txpowertrackingindex--;
if (p->rfa_txpowertrackingindex_real > 4) { if (p->rfa_txpowertrackingindex_real > 4) {
p->rfa_txpowertrackingindex_real--; p->rfa_txpowertrackingindex_real--;
rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord, bMaskDWord,
dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]); dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
} }
p->rfc_txpowertrackingindex--; p->rfc_txpowertrackingindex--;
if (p->rfc_txpowertrackingindex_real > 4) { if (p->rfc_txpowertrackingindex_real > 4) {
p->rfc_txpowertrackingindex_real--; p->rfc_txpowertrackingindex_real--;
rtl8192_setBBreg(dev, rtl92e_set_bb_reg(dev,
rOFDM0_XCTxIQImbalance, rOFDM0_XCTxIQImbalance,
bMaskDWord, bMaskDWord,
dm_tx_bb_gain[p->rfc_txpowertrackingindex_real]); dm_tx_bb_gain[p->rfc_txpowertrackingindex_real]);
} }
} else { } else {
rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord, bMaskDWord,
dm_tx_bb_gain[4]); dm_tx_bb_gain[4]);
rtl8192_setBBreg(dev, rtl92e_set_bb_reg(dev,
rOFDM0_XCTxIQImbalance, rOFDM0_XCTxIQImbalance,
bMaskDWord, dm_tx_bb_gain[4]); bMaskDWord, dm_tx_bb_gain[4]);
} }
} else { } else {
if (p->rfa_txpowertrackingindex > 0) { if (p->rfa_txpowertrackingindex > 0) {
p->rfa_txpowertrackingindex--; p->rfa_txpowertrackingindex--;
if (p->rfa_txpowertrackingindex_real > 4) { if (p->rfa_txpowertrackingindex_real > 4) {
p->rfa_txpowertrackingindex_real--; p->rfa_txpowertrackingindex_real--;
rtl8192_setBBreg(dev, rtl92e_set_bb_reg(dev,
rOFDM0_XATxIQImbalance, rOFDM0_XATxIQImbalance,
bMaskDWord, bMaskDWord,
dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]); dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
} }
} else { } else {
rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord, dm_tx_bb_gain[4]); bMaskDWord, dm_tx_bb_gain[4]);
} }
} }
} }
@ -608,36 +608,33 @@ static void dm_tx_update_tssi_strong_signal(struct net_device *dev, u8 RF_Type)
(p->rfc_txpowertrackingindex < TxBBGainTableLength - 1)) { (p->rfc_txpowertrackingindex < TxBBGainTableLength - 1)) {
p->rfa_txpowertrackingindex++; p->rfa_txpowertrackingindex++;
p->rfa_txpowertrackingindex_real++; p->rfa_txpowertrackingindex_real++;
rtl8192_setBBreg(dev, rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
rOFDM0_XATxIQImbalance, bMaskDWord,
bMaskDWord, dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
p->rfc_txpowertrackingindex++; p->rfc_txpowertrackingindex++;
p->rfc_txpowertrackingindex_real++; p->rfc_txpowertrackingindex_real++;
rtl8192_setBBreg(dev, rtl92e_set_bb_reg(dev, rOFDM0_XCTxIQImbalance,
rOFDM0_XCTxIQImbalance, bMaskDWord,
bMaskDWord, dm_tx_bb_gain[p->rfc_txpowertrackingindex_real]);
dm_tx_bb_gain[p->rfc_txpowertrackingindex_real]);
} else { } else {
rtl8192_setBBreg(dev, rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
rOFDM0_XATxIQImbalance, bMaskDWord,
bMaskDWord, dm_tx_bb_gain[TxBBGainTableLength - 1]);
dm_tx_bb_gain[TxBBGainTableLength - 1]); rtl92e_set_bb_reg(dev, rOFDM0_XCTxIQImbalance,
rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord,
bMaskDWord, dm_tx_bb_gain[TxBBGainTableLength - 1]);
dm_tx_bb_gain[TxBBGainTableLength - 1]);
} }
} else { } else {
if (p->rfa_txpowertrackingindex < (TxBBGainTableLength - 1)) { if (p->rfa_txpowertrackingindex < (TxBBGainTableLength - 1)) {
p->rfa_txpowertrackingindex++; p->rfa_txpowertrackingindex++;
p->rfa_txpowertrackingindex_real++; p->rfa_txpowertrackingindex_real++;
rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord, bMaskDWord,
dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]); dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
} else { } else {
rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
bMaskDWord, bMaskDWord,
dm_tx_bb_gain[TxBBGainTableLength - 1]); dm_tx_bb_gain[TxBBGainTableLength - 1]);
} }
} }
} }
@ -941,8 +938,8 @@ static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device *dev)
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
if (priv->OFDM_index[0] != tmpOFDMindex) { if (priv->OFDM_index[0] != tmpOFDMindex) {
priv->OFDM_index[0] = tmpOFDMindex; priv->OFDM_index[0] = tmpOFDMindex;
rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance, bMaskDWord,
OFDMSwingTable[priv->OFDM_index[0]]); OFDMSwingTable[priv->OFDM_index[0]]);
RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n", RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
priv->OFDM_index[0], priv->OFDM_index[0],
OFDMSwingTable[priv->OFDM_index[0]]); OFDMSwingTable[priv->OFDM_index[0]]);
@ -1073,30 +1070,30 @@ static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14)
TempVal = (u32)(dm_cck_tx_bb_gain[attenuation][0] + TempVal = (u32)(dm_cck_tx_bb_gain[attenuation][0] +
(dm_cck_tx_bb_gain[attenuation][1] << 8)); (dm_cck_tx_bb_gain[attenuation][1] << 8));
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); rtl92e_set_bb_reg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
TempVal = (u32)((dm_cck_tx_bb_gain[attenuation][2]) + TempVal = (u32)((dm_cck_tx_bb_gain[attenuation][2]) +
(dm_cck_tx_bb_gain[attenuation][3] << 8) + (dm_cck_tx_bb_gain[attenuation][3] << 8) +
(dm_cck_tx_bb_gain[attenuation][4] << 16)+ (dm_cck_tx_bb_gain[attenuation][4] << 16)+
(dm_cck_tx_bb_gain[attenuation][5] << 24)); (dm_cck_tx_bb_gain[attenuation][5] << 24));
rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); rtl92e_set_bb_reg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
TempVal = (u32)(dm_cck_tx_bb_gain[attenuation][6] + TempVal = (u32)(dm_cck_tx_bb_gain[attenuation][6] +
(dm_cck_tx_bb_gain[attenuation][7] << 8)); (dm_cck_tx_bb_gain[attenuation][7] << 8));
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); rtl92e_set_bb_reg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
} else { } else {
TempVal = (u32)((dm_cck_tx_bb_gain_ch14[attenuation][0]) + TempVal = (u32)((dm_cck_tx_bb_gain_ch14[attenuation][0]) +
(dm_cck_tx_bb_gain_ch14[attenuation][1] << 8)); (dm_cck_tx_bb_gain_ch14[attenuation][1] << 8));
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); rtl92e_set_bb_reg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
TempVal = (u32)((dm_cck_tx_bb_gain_ch14[attenuation][2]) + TempVal = (u32)((dm_cck_tx_bb_gain_ch14[attenuation][2]) +
(dm_cck_tx_bb_gain_ch14[attenuation][3] << 8) + (dm_cck_tx_bb_gain_ch14[attenuation][3] << 8) +
(dm_cck_tx_bb_gain_ch14[attenuation][4] << 16)+ (dm_cck_tx_bb_gain_ch14[attenuation][4] << 16)+
(dm_cck_tx_bb_gain_ch14[attenuation][5] << 24)); (dm_cck_tx_bb_gain_ch14[attenuation][5] << 24));
rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); rtl92e_set_bb_reg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
TempVal = (u32)((dm_cck_tx_bb_gain_ch14[attenuation][6]) + TempVal = (u32)((dm_cck_tx_bb_gain_ch14[attenuation][6]) +
(dm_cck_tx_bb_gain_ch14[attenuation][7] << 8)); (dm_cck_tx_bb_gain_ch14[attenuation][7] << 8));
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); rtl92e_set_bb_reg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
} }
} }
@ -1110,7 +1107,7 @@ static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev,
if (!bInCH14) { if (!bInCH14) {
TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] + TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
(CCKSwingTable_Ch1_Ch13[priv->CCK_index][1] << 8); (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1] << 8);
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); rtl92e_set_bb_reg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
RT_TRACE(COMP_POWER_TRACKING, RT_TRACE(COMP_POWER_TRACKING,
"CCK not chnl 14, reg 0x%x = 0x%x\n", rCCK0_TxFilter1, "CCK not chnl 14, reg 0x%x = 0x%x\n", rCCK0_TxFilter1,
TempVal); TempVal);
@ -1118,14 +1115,14 @@ static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev,
(CCKSwingTable_Ch1_Ch13[priv->CCK_index][3] << 8) + (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3] << 8) +
(CCKSwingTable_Ch1_Ch13[priv->CCK_index][4] << 16)+ (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4] << 16)+
(CCKSwingTable_Ch1_Ch13[priv->CCK_index][5] << 24); (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5] << 24);
rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); rtl92e_set_bb_reg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
RT_TRACE(COMP_POWER_TRACKING, RT_TRACE(COMP_POWER_TRACKING,
"CCK not chnl 14, reg 0x%x = 0x%x\n", rCCK0_TxFilter2, "CCK not chnl 14, reg 0x%x = 0x%x\n", rCCK0_TxFilter2,
TempVal); TempVal);
TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] + TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
(CCKSwingTable_Ch1_Ch13[priv->CCK_index][7] << 8); (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7] << 8);
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); rtl92e_set_bb_reg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
RT_TRACE(COMP_POWER_TRACKING, RT_TRACE(COMP_POWER_TRACKING,
"CCK not chnl 14, reg 0x%x = 0x%x\n", rCCK0_DebugPort, "CCK not chnl 14, reg 0x%x = 0x%x\n", rCCK0_DebugPort,
TempVal); TempVal);
@ -1133,20 +1130,20 @@ static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev,
TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] + TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] +
(CCKSwingTable_Ch14[priv->CCK_index][1] << 8); (CCKSwingTable_Ch14[priv->CCK_index][1] << 8);
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); rtl92e_set_bb_reg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
rCCK0_TxFilter1, TempVal); rCCK0_TxFilter1, TempVal);
TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] + TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] +
(CCKSwingTable_Ch14[priv->CCK_index][3] << 8) + (CCKSwingTable_Ch14[priv->CCK_index][3] << 8) +
(CCKSwingTable_Ch14[priv->CCK_index][4] << 16)+ (CCKSwingTable_Ch14[priv->CCK_index][4] << 16)+
(CCKSwingTable_Ch14[priv->CCK_index][5] << 24); (CCKSwingTable_Ch14[priv->CCK_index][5] << 24);
rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); rtl92e_set_bb_reg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
rCCK0_TxFilter2, TempVal); rCCK0_TxFilter2, TempVal);
TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] + TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] +
(CCKSwingTable_Ch14[priv->CCK_index][7]<<8); (CCKSwingTable_Ch14[priv->CCK_index][7]<<8);
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); rtl92e_set_bb_reg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
rCCK0_DebugPort, TempVal); rCCK0_DebugPort, TempVal);
} }
@ -1167,8 +1164,8 @@ static void dm_txpower_reset_recovery(struct net_device *dev)
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n"); RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance, bMaskDWord,
dm_tx_bb_gain[priv->rfa_txpowertrackingindex]); dm_tx_bb_gain[priv->rfa_txpowertrackingindex]);
RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n", RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",
dm_tx_bb_gain[priv->rfa_txpowertrackingindex]); dm_tx_bb_gain[priv->rfa_txpowertrackingindex]);
RT_TRACE(COMP_POWER_TRACKING, RT_TRACE(COMP_POWER_TRACKING,
@ -1182,8 +1179,8 @@ static void dm_txpower_reset_recovery(struct net_device *dev)
priv->CCKPresentAttentuation); priv->CCKPresentAttentuation);
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, rtl92e_set_bb_reg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord,
dm_tx_bb_gain[priv->rfc_txpowertrackingindex]); dm_tx_bb_gain[priv->rfc_txpowertrackingindex]);
RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n", RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",
dm_tx_bb_gain[priv->rfc_txpowertrackingindex]); dm_tx_bb_gain[priv->rfc_txpowertrackingindex]);
RT_TRACE(COMP_POWER_TRACKING, RT_TRACE(COMP_POWER_TRACKING,
@ -1231,18 +1228,18 @@ static void dm_bb_initialgain_restore(struct net_device *dev)
if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
return; return;
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, bit_mask,
(u32)priv->initgain_backup.xaagccore1); (u32)priv->initgain_backup.xaagccore1);
rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, bit_mask,
(u32)priv->initgain_backup.xbagccore1); (u32)priv->initgain_backup.xbagccore1);
rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, bit_mask,
(u32)priv->initgain_backup.xcagccore1); (u32)priv->initgain_backup.xcagccore1);
rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, bit_mask,
(u32)priv->initgain_backup.xdagccore1); (u32)priv->initgain_backup.xdagccore1);
bit_mask = bMaskByte2; bit_mask = bMaskByte2;
rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, rtl92e_set_bb_reg(dev, rCCK0_CCA, bit_mask,
(u32)priv->initgain_backup.cca); (u32)priv->initgain_backup.cca);
RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n", RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",
priv->initgain_backup.xaagccore1); priv->initgain_backup.xaagccore1);
@ -1254,7 +1251,7 @@ static void dm_bb_initialgain_restore(struct net_device *dev)
priv->initgain_backup.xdagccore1); priv->initgain_backup.xdagccore1);
RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n", RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",
priv->initgain_backup.cca); priv->initgain_backup.cca);
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1);
} }
@ -1278,7 +1275,7 @@ static void dm_bb_initialgain_backup(struct net_device *dev)
if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
return; return;
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
priv->initgain_backup.xaagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1, bit_mask); priv->initgain_backup.xaagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1, bit_mask);
priv->initgain_backup.xbagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1, bit_mask); priv->initgain_backup.xbagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1, bit_mask);
priv->initgain_backup.xcagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1, bit_mask); priv->initgain_backup.xcagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1, bit_mask);
@ -1375,7 +1372,7 @@ static void dm_ctrl_initgain_byrssi_by_driverrssi(
fw_dig = 0; fw_dig = 0;
if (fw_dig <= 3) { if (fw_dig <= 3) {
for (i = 0; i < 3; i++) for (i = 0; i < 3; i++)
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
fw_dig++; fw_dig++;
dm_digtable.dig_state = DM_STA_DIG_OFF; dm_digtable.dig_state = DM_STA_DIG_OFF;
} }
@ -1409,7 +1406,7 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
if (dm_digtable.dig_algorithm_switch) { if (dm_digtable.dig_algorithm_switch) {
dm_digtable.dig_state = DM_STA_DIG_MAX; dm_digtable.dig_state = DM_STA_DIG_MAX;
for (i = 0; i < 3; i++) for (i = 0; i < 3; i++)
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1);
dm_digtable.dig_algorithm_switch = 0; dm_digtable.dig_algorithm_switch = 0;
} }
@ -1428,7 +1425,7 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX; dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
dm_digtable.dig_state = DM_STA_DIG_OFF; dm_digtable.dig_state = DM_STA_DIG_OFF;
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17); write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
@ -1479,7 +1476,7 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
write_nic_byte(dev, 0xa0a, 0xcd); write_nic_byte(dev, 0xa0a, 0xcd);
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1);
} }
dm_ctrl_initgain_byrssi_highpwr(dev); dm_ctrl_initgain_byrssi_highpwr(dev);
} }
@ -2115,10 +2112,10 @@ static void dm_rxpath_sel_byrssi(struct net_device *dev)
DM_RxPathSelTable.diff_TH) { DM_RxPathSelTable.diff_TH) {
DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] =
tmp_max_rssi+5; tmp_max_rssi+5;
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable,
0x1<<min_rssi_index, 0x0); 0x1<<min_rssi_index, 0x0);
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable,
0x1<<min_rssi_index, 0x0); 0x1<<min_rssi_index, 0x0);
disabled_rf_cnt++; disabled_rf_cnt++;
} }
if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_1) { if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_1) {
@ -2132,8 +2129,8 @@ static void dm_rxpath_sel_byrssi(struct net_device *dev)
if (update_cck_rx_path) { if (update_cck_rx_path) {
DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2) | DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2) |
(cck_optional_Rx); (cck_optional_Rx);
rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, rtl92e_set_bb_reg(dev, rCCK0_AFESetting, 0x0f000000,
DM_RxPathSelTable.cck_Rx_path); DM_RxPathSelTable.cck_Rx_path);
} }
if (DM_RxPathSelTable.disabledRF) { if (DM_RxPathSelTable.disabledRF) {
@ -2141,12 +2138,12 @@ static void dm_rxpath_sel_byrssi(struct net_device *dev)
if ((DM_RxPathSelTable.disabledRF>>i) & 0x1) { if ((DM_RxPathSelTable.disabledRF>>i) & 0x1) {
if (tmp_max_rssi >= if (tmp_max_rssi >=
DM_RxPathSelTable.rf_enable_rssi_th[i]) { DM_RxPathSelTable.rf_enable_rssi_th[i]) {
rtl8192_setBBreg(dev, rtl92e_set_bb_reg(dev,
rOFDM0_TRxPathEnable, 0x1 << i, rOFDM0_TRxPathEnable,
0x1); 0x1 << i, 0x1);
rtl8192_setBBreg(dev, rtl92e_set_bb_reg(dev,
rOFDM1_TRxPathEnable, rOFDM1_TRxPathEnable,
0x1 << i, 0x1); 0x1 << i, 0x1);
DM_RxPathSelTable.rf_enable_rssi_th[i] DM_RxPathSelTable.rf_enable_rssi_th[i]
= 100; = 100;
disabled_rf_cnt--; disabled_rf_cnt--;