Merge "msm: kgsl: Disable RB sampler data path optimization"

Documentation/devicetree/bindings/gpu/adreno.txt

@@ -152,6 +152,8 @@ GPU Quirks:
 - qcom,gpu-quirk-fault-detect-mask:
 				Mask out RB1-3 activity signals from HW hang
 				detection logic
+- qcom,gpu-quirk-dp2clockgating-disable:
+				Disable RB sampler data path clock gating optimization
 
 The following properties are optional as collecting data via coresight might
 not be supported for every chipset. The documentation for coresight

drivers/gpu/msm/a5xx_reg.h

@@ -561,6 +561,7 @@
 
 
 /* RB registers */
+#define A5XX_RB_DBG_ECO_CNT                 0xCC4
 #define A5XX_RB_ADDR_MODE_CNTL              0xCC5
 #define A5XX_RB_MODE_CNTL                   0xCC6
 #define A5XX_RB_PERFCTR_RB_SEL_0            0xCD0

drivers/gpu/msm/adreno.c

@@ -825,6 +825,8 @@ static struct {
 	 { ADRENO_QUIRK_IOMMU_SYNC, "qcom,gpu-quirk-iommu-sync" },
 	 { ADRENO_QUIRK_CRITICAL_PACKETS, "qcom,gpu-quirk-critical-packets" },
 	 { ADRENO_QUIRK_FAULT_DETECT_MASK, "qcom,gpu-quirk-fault-detect-mask" },
+	 { ADRENO_QUIRK_DISABLE_RB_DP2CLOCKGATING,
+			"qcom,gpu-quirk-dp2clockgating-disable" },
 };
 
 static int adreno_of_get_power(struct adreno_device *adreno_dev,

drivers/gpu/msm/adreno.h

@@ -121,6 +121,8 @@
 #define ADRENO_QUIRK_CRITICAL_PACKETS BIT(2)
 /* Mask out RB1-3 activity signals from HW hang detection logic */
 #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(3)
+/* Disable RB sampler datapath clock gating optimization */
+#define ADRENO_QUIRK_DISABLE_RB_DP2CLOCKGATING BIT(4)
 
 /* Flags to control command packet settings */
 #define KGSL_CMD_FLAGS_NONE             0

drivers/gpu/msm/adreno_a5xx.c

@@ -1836,6 +1836,13 @@ static void a5xx_start(struct adreno_device *adreno_dev)
 			kgsl_regrmw(device, A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));
 	}
 
+	if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_DISABLE_RB_DP2CLOCKGATING)) {
+		/*
+		 * Disable RB sampler datapath DP2 clock gating
+		 * optimization for 1-SP GPU's, by default it is enabled.
+		 */
+		kgsl_regrmw(device, A5XX_RB_DBG_ECO_CNT, 0, (1 << 9));
+	}
 	/* Set the USE_RETENTION_FLOPS chicken bit */
 	kgsl_regwrite(device, A5XX_CP_CHICKEN_DBG, 0x02000000);