Nomadik DT and clock work:
- Lee Jones' pinctrl compat ontology patches - A real clock driver for the Nomadik, 100% DT-based - Device tree changes for the Nomadik clocks -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.13 (GNU/Linux) iQIcBAABAgAGBQJRwrp4AAoJEEEQszewGV1zLVkP/1c/zyS4gOjMZLf2aqhT/KAR K5NRuNQgWnzLtZiEV/sEfiG1aXdJIRUiRwYYOBm//DiTduEURh60H4xIU+BgwaA8 FjwZw52y9iFp92uASz0IGyBoWc3x8poEPVgM9qStSMKLPdpU0IvsYxRi9reFUtM3 XQrs8geZ2Twjzwu81655D/aIbps1dhN6JvUtclhHKdcqcISndOk8LGqTPLhqo7R1 nBmKMmM04uQz/sov/iKiOG9LeUPgJwBzgdDtP/qgmGMDbZqMF9Hy6ErNYL4X2iNa wzJNl17n0Ml2Z1qoB+WCrpF7sNRKj66ee0T6K0L4MpIHM4NsXuRg0hV7Hzkzd5aY FBSNu02m9k7Cz8RHlqd1ova1deqCsER04gIF/06kyqWq2g+l8ACeAVxUOHHD/cnr JX4nNfmDowzKCneJVa+CWmh9DWIzAocCFTEBRb4DkHHZypWzR7OKXAI/L1mzDtV+ n2uKu9lQt/0dzVv87fxh4cBWswsl28ADJdc9l7S4PILkYTYBL7oz/UXL6A/xBZY1 NBsIHp23/QJiGVXkbKeMAjt7kTVQIPtti/NxWAjGrJcEc5BTT8031SLnOrdTLmtD IixP6r0ZaTHKpYkgEygZHOYrcOh4TbbQ57Cb0cuzl/Ph/u7RgtaYfpbRumhHTbUM rHEvMBVGgN7dzOoJ+/oS =0yyI -----END PGP SIGNATURE----- Merge tag 'nomadik-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt From Linus Walleij: Nomadik DT and clock work: - Lee Jones' pinctrl compat ontology patches - A real clock driver for the Nomadik, 100% DT-based - Device tree changes for the Nomadik clocks * tag 'nomadik-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: nomadik: add the new clocks to the device tree clk: nomadik: implement the Nomadik clocks properly pinctrl/nomadik: Standardise Pinctrl compat string for Nomadik based platforms ARM: nomadik: Standardise Nomadik STN8815 based Pinctrl compat string in the DTS Conflicts: arch/arm/boot/dts/ste-nomadik-s8815.dts Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
15f4b11b0f
5 changed files with 1124 additions and 42 deletions
104
Documentation/devicetree/bindings/clock/st,nomadik.txt
Normal file
104
Documentation/devicetree/bindings/clock/st,nomadik.txt
Normal file
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@ -0,0 +1,104 @@
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ST Microelectronics Nomadik SRC System Reset and Control
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The Nomadik SRC controller is responsible of controlling chrystals,
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PLLs and clock gates.
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Required properties for the SRC node:
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- compatible: must be "stericsson,nomadik-src"
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- reg: must contain the SRC register base and size
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Optional properties for the SRC node:
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- disable-sxtalo: if present this will disable the SXTALO
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i.e. the driver output for the slow 32kHz chrystal, if the
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board has its own circuitry for providing this oscillator
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- disable-mxtal: if present this will disable the MXTALO,
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i.e. the driver output for the main (~19.2 MHz) chrystal,
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if the board has its own circuitry for providing this
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osciallator
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PLL nodes: these nodes represent the two PLLs on the system,
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which should both have the main chrystal, represented as a
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fixed frequency clock, as parent.
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Required properties for the two PLL nodes:
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- compatible: must be "st,nomadik-pll-clock"
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- clock-cells: must be 0
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- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
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- clocks: this clock will have main chrystal as parent
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HCLK nodes: these represent the clock gates on individual
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lines from the HCLK clock tree and the gate for individual
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lines from the PCLK clock tree.
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Requires properties for the HCLK nodes:
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- compatible: must be "st,nomadik-hclk-clock"
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- clock-cells: must be 0
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- clock-id: must be the clock ID from 0 to 63 according to
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this table:
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0: HCLKDMA0
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1: HCLKSMC
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2: HCLKSDRAM
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3: HCLKDMA1
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4: HCLKCLCD
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5: PCLKIRDA
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6: PCLKSSP
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7: PCLKUART0
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8: PCLKSDI
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9: PCLKI2C0
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10: PCLKI2C1
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11: PCLKUART1
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12: PCLMSP0
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13: HCLKUSB
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14: HCLKDIF
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15: HCLKSAA
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16: HCLKSVA
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17: PCLKHSI
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18: PCLKXTI
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19: PCLKUART2
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20: PCLKMSP1
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21: PCLKMSP2
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22: PCLKOWM
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23: HCLKHPI
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24: PCLKSKE
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25: PCLKHSEM
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26: HCLK3D
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27: HCLKHASH
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28: HCLKCRYP
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29: PCLKMSHC
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30: HCLKUSBM
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31: HCLKRNG
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(32, 33, 34, 35 RESERVED)
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36: CLDCLK
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37: IRDACLK
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38: SSPICLK
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39: UART0CLK
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40: SDICLK
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41: I2C0CLK
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42: I2C1CLK
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43: UART1CLK
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44: MSPCLK0
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45: USBCLK
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46: DIFCLK
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47: IPI2CCLK
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48: IPBMCCLK
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49: HSICLKRX
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50: HSICLKTX
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51: UART2CLK
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52: MSPCLK1
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53: MSPCLK2
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54: OWMCLK
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(55 RESERVED)
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56: SKECLK
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(57 RESERVED)
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58: 3DCLK
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59: PCLKMSP3
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60: MSPCLK3
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61: MSHCCLK
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62: USBMCLK
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63: RNGCCLK
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@ -22,6 +22,12 @@
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};
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};
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};
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};
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src@101e0000 {
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/* These chrystal drivers are not used on this board */
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disable-sxtalo;
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disable-mxtalo;
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};
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pinctrl {
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pinctrl {
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/* Hog CD pins */
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/* Hog CD pins */
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pinctrl-names = "default";
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pinctrl-names = "default";
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@ -93,7 +93,7 @@
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};
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};
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pinctrl {
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pinctrl {
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compatible = "stericsson,nmk-pinctrl-stn8815";
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compatible = "stericsson,stn8815-pinctrl";
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/* Pin configurations */
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/* Pin configurations */
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uart0 {
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uart0 {
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uart0_default_mux: uart0_mux {
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uart0_default_mux: uart0_mux {
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@ -168,15 +168,19 @@
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src: src@101e0000 {
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src: src@101e0000 {
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compatible = "stericsson,nomadik-src";
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compatible = "stericsson,nomadik-src";
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reg = <0x101e0000 0x1000>;
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reg = <0x101e0000 0x1000>;
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clocks {
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disable-sxtalo;
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disable-mxtalo;
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/*
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/*
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* Dummy clock for primecells
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* MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
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* that is parent of TIMCLK, PLL1 and PLL2
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*/
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*/
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pclk: pclk@0 {
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mxtal: mxtal@19.2M {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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compatible = "fixed-clock";
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clock-frequency = <0>;
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clock-frequency = <19200000>;
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};
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};
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/*
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/*
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* The 2.4 MHz TIMCLK reference clock is active at
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* The 2.4 MHz TIMCLK reference clock is active at
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* boot time, this is actually the MXTALCLK @19.2 MHz
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* boot time, this is actually the MXTALCLK @19.2 MHz
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@ -185,20 +189,443 @@
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*/
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*/
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timclk: timclk@2.4M {
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timclk: timclk@2.4M {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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compatible = "fixed-factor-clock";
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clock-frequency = <2400000>;
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clock-div = <8>;
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clock-mult = <1>;
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clocks = <&mxtal>;
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};
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/* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
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pll1: pll1@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-pll-clock";
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pll-id = <1>;
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clocks = <&mxtal>;
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};
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/* HCLK divides the PLL1 with 1,2,3 or 4 */
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hclk: hclk@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-hclk-clock";
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clocks = <&pll1>;
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};
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/* The PCLK domain uses HCLK right off */
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&hclk>;
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};
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/* PLL2 is usually 864 MHz and divided into a few fixed rates */
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pll2: pll2@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-pll-clock";
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pll-id = <2>;
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clocks = <&mxtal>;
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};
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clk216: clk216@216M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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clk108: clk108@108M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&clk216>;
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};
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clk72: clk72@72M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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/* The data sheet does not say how this is derived */
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clock-div = <12>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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};
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/*
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* At boot time, PLL2 is set to generate a set of
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* fixed clocks, one of them is CLK48, the 48 MHz
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* clock, routed to the UART, MMC/SD, I2C, IrDA,
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* USB and SSP blocks.
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*/
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clk48: clk48@48M {
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clk48: clk48@48M {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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compatible = "fixed-factor-clock";
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clock-frequency = <48000000>;
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/* The data sheet does not say how this is derived */
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clock-div = <18>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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};
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clk27: clk27@27M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&clk108>;
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};
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/* This apparently exists as well */
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ulpiclk: ulpiclk@60M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <60000000>;
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};
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/*
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* IP AMBA bus clocks, driving the bus side of the
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* peripheral clocking, clock gates.
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*/
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hclkdma0: hclkdma0@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <0>;
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clocks = <&hclk>;
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};
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hclksmc: hclksmc@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <1>;
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clocks = <&hclk>;
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};
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hclksdram: hclksdram@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <2>;
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clocks = <&hclk>;
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};
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hclkdma1: hclkdma1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <3>;
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clocks = <&hclk>;
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};
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hclkclcd: hclkclcd@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
|
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clock-id = <4>;
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clocks = <&hclk>;
|
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};
|
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pclkirda: pclkirda@48M {
|
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <5>;
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clocks = <&pclk>;
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};
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pclkssp: pclkssp@48M {
|
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <6>;
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clocks = <&pclk>;
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};
|
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|
pclkuart0: pclkuart0@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
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compatible = "st,nomadik-src-clock";
|
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clock-id = <7>;
|
||||||
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clocks = <&pclk>;
|
||||||
|
};
|
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pclksdi: pclksdi@48M {
|
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|
#clock-cells = <0>;
|
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|
compatible = "st,nomadik-src-clock";
|
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|
clock-id = <8>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
pclki2c0: pclki2c0@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <9>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
pclki2c1: pclki2c1@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <10>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
pclkuart1: pclkuart1@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <11>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
pclkmsp0: pclkmsp0@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <12>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
hclkusb: hclkusb@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <13>;
|
||||||
|
clocks = <&hclk>;
|
||||||
|
};
|
||||||
|
hclkdif: hclkdif@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <14>;
|
||||||
|
clocks = <&hclk>;
|
||||||
|
};
|
||||||
|
hclksaa: hclksaa@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <15>;
|
||||||
|
clocks = <&hclk>;
|
||||||
|
};
|
||||||
|
hclksva: hclksva@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <16>;
|
||||||
|
clocks = <&hclk>;
|
||||||
|
};
|
||||||
|
pclkhsi: pclkhsi@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <17>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
pclkxti: pclkxti@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <18>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
pclkuart2: pclkuart2@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <19>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
pclkmsp1: pclkmsp1@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <20>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
pclkmsp2: pclkmsp2@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <21>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
pclkowm: pclkowm@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <22>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
hclkhpi: hclkhpi@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <23>;
|
||||||
|
clocks = <&hclk>;
|
||||||
|
};
|
||||||
|
pclkske: pclkske@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <24>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
pclkhsem: pclkhsem@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <25>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
hclk3d: hclk3d@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <26>;
|
||||||
|
clocks = <&hclk>;
|
||||||
|
};
|
||||||
|
hclkhash: hclkhash@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <27>;
|
||||||
|
clocks = <&hclk>;
|
||||||
|
};
|
||||||
|
hclkcryp: hclkcryp@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <28>;
|
||||||
|
clocks = <&hclk>;
|
||||||
|
};
|
||||||
|
pclkmshc: pclkmshc@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <29>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
hclkusbm: hclkusbm@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <30>;
|
||||||
|
clocks = <&hclk>;
|
||||||
|
};
|
||||||
|
hclkrng: hclkrng@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <31>;
|
||||||
|
clocks = <&hclk>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* IP kernel clocks */
|
||||||
|
clcdclk: clcdclk@0 {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <36>;
|
||||||
|
clocks = <&clk72 &clk48>;
|
||||||
|
};
|
||||||
|
irdaclk: irdaclk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <37>;
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
sspiclk: sspiclk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <38>;
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
uart0clk: uart0clk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <39>;
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
sdiclk: sdiclk@48M {
|
||||||
|
/* Also called MCCLK in some documents */
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <40>;
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
i2c0clk: i2c0clk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <41>;
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
i2c1clk: i2c1clk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <42>;
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
uart1clk: uart1clk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <43>;
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
mspclk0: mspclk0@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <44>;
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
usbclk: usbclk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <45>;
|
||||||
|
clocks = <&clk48>; /* 48 MHz not ULPI */
|
||||||
|
};
|
||||||
|
difclk: difclk@72M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <46>;
|
||||||
|
clocks = <&clk72>;
|
||||||
|
};
|
||||||
|
ipi2cclk: ipi2cclk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <47>;
|
||||||
|
clocks = <&clk48>; /* Guess */
|
||||||
|
};
|
||||||
|
ipbmcclk: ipbmcclk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <48>;
|
||||||
|
clocks = <&clk48>; /* Guess */
|
||||||
|
};
|
||||||
|
hsiclkrx: hsiclkrx@216M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <49>;
|
||||||
|
clocks = <&clk216>;
|
||||||
|
};
|
||||||
|
hsiclktx: hsiclktx@108M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <50>;
|
||||||
|
clocks = <&clk108>;
|
||||||
|
};
|
||||||
|
uart2clk: uart2clk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <51>;
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
mspclk1: mspclk1@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <52>;
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
mspclk2: mspclk2@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <53>;
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
owmclk: owmclk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <54>;
|
||||||
|
clocks = <&clk48>; /* Guess */
|
||||||
|
};
|
||||||
|
skeclk: skeclk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <56>;
|
||||||
|
clocks = <&clk48>; /* Guess */
|
||||||
|
};
|
||||||
|
x3dclk: x3dclk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <58>;
|
||||||
|
clocks = <&clk48>; /* Guess */
|
||||||
|
};
|
||||||
|
pclkmsp3: pclkmsp3@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <59>;
|
||||||
|
clocks = <&pclk>;
|
||||||
|
};
|
||||||
|
mspclk3: mspclk3@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <60>;
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
mshcclk: mshcclk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <61>;
|
||||||
|
clocks = <&clk48>; /* Guess */
|
||||||
|
};
|
||||||
|
usbmclk: usbmclk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <62>;
|
||||||
|
/* Stated as "48 MHz not ULPI clock" */
|
||||||
|
clocks = <&clk48>;
|
||||||
|
};
|
||||||
|
rngcclk: rngcclk@48M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "st,nomadik-src-clock";
|
||||||
|
clock-id = <63>;
|
||||||
|
clocks = <&clk48>; /* Guess */
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -212,7 +639,7 @@
|
||||||
<0x41000000 0x2000>, /* NAND Base ADDR */
|
<0x41000000 0x2000>, /* NAND Base ADDR */
|
||||||
<0x40800000 0x2000>; /* NAND Base CMD */
|
<0x40800000 0x2000>; /* NAND Base CMD */
|
||||||
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
|
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
|
||||||
clocks = <&pclk>;
|
clocks = <&hclksmc>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
partition@0 {
|
partition@0 {
|
||||||
|
|
@ -334,7 +761,7 @@
|
||||||
reg = <0x101fd000 0x1000>;
|
reg = <0x101fd000 0x1000>;
|
||||||
interrupt-parent = <&vica>;
|
interrupt-parent = <&vica>;
|
||||||
interrupts = <12>;
|
interrupts = <12>;
|
||||||
clocks = <&clk48>, <&pclk>;
|
clocks = <&uart0clk>, <&pclkuart0>;
|
||||||
clock-names = "uartclk", "apb_pclk";
|
clock-names = "uartclk", "apb_pclk";
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&uart0_default_mux>;
|
pinctrl-0 = <&uart0_default_mux>;
|
||||||
|
|
@ -345,7 +772,7 @@
|
||||||
reg = <0x101fb000 0x1000>;
|
reg = <0x101fb000 0x1000>;
|
||||||
interrupt-parent = <&vica>;
|
interrupt-parent = <&vica>;
|
||||||
interrupts = <17>;
|
interrupts = <17>;
|
||||||
clocks = <&clk48>, <&pclk>;
|
clocks = <&uart1clk>, <&pclkuart1>;
|
||||||
clock-names = "uartclk", "apb_pclk";
|
clock-names = "uartclk", "apb_pclk";
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&uart1_default_mux>;
|
pinctrl-0 = <&uart1_default_mux>;
|
||||||
|
|
@ -356,7 +783,7 @@
|
||||||
reg = <0x101f2000 0x1000>;
|
reg = <0x101f2000 0x1000>;
|
||||||
interrupt-parent = <&vica>;
|
interrupt-parent = <&vica>;
|
||||||
interrupts = <28>;
|
interrupts = <28>;
|
||||||
clocks = <&clk48>, <&pclk>;
|
clocks = <&uart2clk>, <&pclkuart2>;
|
||||||
clock-names = "uartclk", "apb_pclk";
|
clock-names = "uartclk", "apb_pclk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
@ -364,7 +791,7 @@
|
||||||
rng: rng@101b0000 {
|
rng: rng@101b0000 {
|
||||||
compatible = "arm,primecell";
|
compatible = "arm,primecell";
|
||||||
reg = <0x101b0000 0x1000>;
|
reg = <0x101b0000 0x1000>;
|
||||||
clocks = <&clk48>, <&pclk>;
|
clocks = <&rngcclk>, <&hclkrng>;
|
||||||
clock-names = "rng", "apb_pclk";
|
clock-names = "rng", "apb_pclk";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -380,7 +807,7 @@
|
||||||
mmcsd: sdi@101f6000 {
|
mmcsd: sdi@101f6000 {
|
||||||
compatible = "arm,pl18x", "arm,primecell";
|
compatible = "arm,pl18x", "arm,primecell";
|
||||||
reg = <0x101f6000 0x1000>;
|
reg = <0x101f6000 0x1000>;
|
||||||
clocks = <&clk48>, <&pclk>;
|
clocks = <&sdiclk>, <&pclksdi>;
|
||||||
clock-names = "mclk", "apb_pclk";
|
clock-names = "mclk", "apb_pclk";
|
||||||
interrupt-parent = <&vica>;
|
interrupt-parent = <&vica>;
|
||||||
interrupts = <22>;
|
interrupts = <22>;
|
||||||
|
|
|
||||||
|
|
@ -1,21 +1,566 @@
|
||||||
|
/*
|
||||||
|
* Nomadik clock implementation
|
||||||
|
* Copyright (C) 2013 ST-Ericsson AB
|
||||||
|
* License terms: GNU General Public License (GPL) version 2
|
||||||
|
* Author: Linus Walleij <linus.walleij@linaro.org>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define pr_fmt(fmt) "Nomadik SRC clocks: " fmt
|
||||||
|
|
||||||
|
#include <linux/bitops.h>
|
||||||
#include <linux/clk.h>
|
#include <linux/clk.h>
|
||||||
#include <linux/clkdev.h>
|
#include <linux/clkdev.h>
|
||||||
#include <linux/err.h>
|
#include <linux/err.h>
|
||||||
#include <linux/io.h>
|
#include <linux/io.h>
|
||||||
#include <linux/clk-provider.h>
|
#include <linux/clk-provider.h>
|
||||||
#include <linux/of.h>
|
#include <linux/of.h>
|
||||||
|
#include <linux/of_address.h>
|
||||||
|
#include <linux/debugfs.h>
|
||||||
|
#include <linux/seq_file.h>
|
||||||
|
#include <linux/spinlock.h>
|
||||||
|
#include <linux/reboot.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The Nomadik clock tree is described in the STN8815A12 DB V4.2
|
* The Nomadik clock tree is described in the STN8815A12 DB V4.2
|
||||||
* reference manual for the chip, page 94 ff.
|
* reference manual for the chip, page 94 ff.
|
||||||
|
* Clock IDs are in the STn8815 Reference Manual table 3, page 27.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static const __initconst struct of_device_id cpu8815_clk_match[] = {
|
#define SRC_CR 0x00U
|
||||||
{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
|
#define SRC_XTALCR 0x0CU
|
||||||
|
#define SRC_XTALCR_XTALTIMEN BIT(20)
|
||||||
|
#define SRC_XTALCR_SXTALDIS BIT(19)
|
||||||
|
#define SRC_XTALCR_MXTALSTAT BIT(2)
|
||||||
|
#define SRC_XTALCR_MXTALEN BIT(1)
|
||||||
|
#define SRC_XTALCR_MXTALOVER BIT(0)
|
||||||
|
#define SRC_PLLCR 0x10U
|
||||||
|
#define SRC_PLLCR_PLLTIMEN BIT(29)
|
||||||
|
#define SRC_PLLCR_PLL2EN BIT(28)
|
||||||
|
#define SRC_PLLCR_PLL1STAT BIT(2)
|
||||||
|
#define SRC_PLLCR_PLL1EN BIT(1)
|
||||||
|
#define SRC_PLLCR_PLL1OVER BIT(0)
|
||||||
|
#define SRC_PLLFR 0x14U
|
||||||
|
#define SRC_PCKEN0 0x24U
|
||||||
|
#define SRC_PCKDIS0 0x28U
|
||||||
|
#define SRC_PCKENSR0 0x2CU
|
||||||
|
#define SRC_PCKSR0 0x30U
|
||||||
|
#define SRC_PCKEN1 0x34U
|
||||||
|
#define SRC_PCKDIS1 0x38U
|
||||||
|
#define SRC_PCKENSR1 0x3CU
|
||||||
|
#define SRC_PCKSR1 0x40U
|
||||||
|
|
||||||
|
/* Lock protecting the SRC_CR register */
|
||||||
|
static DEFINE_SPINLOCK(src_lock);
|
||||||
|
/* Base address of the SRC */
|
||||||
|
static void __iomem *src_base;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct clk_pll1 - Nomadik PLL1 clock
|
||||||
|
* @hw: corresponding clock hardware entry
|
||||||
|
* @id: PLL instance: 1 or 2
|
||||||
|
*/
|
||||||
|
struct clk_pll {
|
||||||
|
struct clk_hw hw;
|
||||||
|
int id;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct clk_src - Nomadik src clock
|
||||||
|
* @hw: corresponding clock hardware entry
|
||||||
|
* @id: the clock ID
|
||||||
|
* @group1: true if the clock is in group1, else it is in group0
|
||||||
|
* @clkbit: bit 0...31 corresponding to the clock in each clock register
|
||||||
|
*/
|
||||||
|
struct clk_src {
|
||||||
|
struct clk_hw hw;
|
||||||
|
int id;
|
||||||
|
bool group1;
|
||||||
|
u32 clkbit;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define to_pll(_hw) container_of(_hw, struct clk_pll, hw)
|
||||||
|
#define to_src(_hw) container_of(_hw, struct clk_src, hw)
|
||||||
|
|
||||||
|
static int pll_clk_enable(struct clk_hw *hw)
|
||||||
|
{
|
||||||
|
struct clk_pll *pll = to_pll(hw);
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
spin_lock(&src_lock);
|
||||||
|
val = readl(src_base + SRC_PLLCR);
|
||||||
|
if (pll->id == 1) {
|
||||||
|
if (val & SRC_PLLCR_PLL1OVER) {
|
||||||
|
val |= SRC_PLLCR_PLL1EN;
|
||||||
|
writel(val, src_base + SRC_PLLCR);
|
||||||
|
}
|
||||||
|
} else if (pll->id == 2) {
|
||||||
|
val |= SRC_PLLCR_PLL2EN;
|
||||||
|
writel(val, src_base + SRC_PLLCR);
|
||||||
|
}
|
||||||
|
spin_unlock(&src_lock);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pll_clk_disable(struct clk_hw *hw)
|
||||||
|
{
|
||||||
|
struct clk_pll *pll = to_pll(hw);
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
spin_lock(&src_lock);
|
||||||
|
val = readl(src_base + SRC_PLLCR);
|
||||||
|
if (pll->id == 1) {
|
||||||
|
if (val & SRC_PLLCR_PLL1OVER) {
|
||||||
|
val &= ~SRC_PLLCR_PLL1EN;
|
||||||
|
writel(val, src_base + SRC_PLLCR);
|
||||||
|
}
|
||||||
|
} else if (pll->id == 2) {
|
||||||
|
val &= ~SRC_PLLCR_PLL2EN;
|
||||||
|
writel(val, src_base + SRC_PLLCR);
|
||||||
|
}
|
||||||
|
spin_unlock(&src_lock);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int pll_clk_is_enabled(struct clk_hw *hw)
|
||||||
|
{
|
||||||
|
struct clk_pll *pll = to_pll(hw);
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
val = readl(src_base + SRC_PLLCR);
|
||||||
|
if (pll->id == 1) {
|
||||||
|
if (val & SRC_PLLCR_PLL1OVER)
|
||||||
|
return !!(val & SRC_PLLCR_PLL1EN);
|
||||||
|
} else if (pll->id == 2) {
|
||||||
|
return !!(val & SRC_PLLCR_PLL2EN);
|
||||||
|
}
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
|
||||||
|
unsigned long parent_rate)
|
||||||
|
{
|
||||||
|
struct clk_pll *pll = to_pll(hw);
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
val = readl(src_base + SRC_PLLFR);
|
||||||
|
|
||||||
|
if (pll->id == 1) {
|
||||||
|
u8 mul;
|
||||||
|
u8 div;
|
||||||
|
|
||||||
|
mul = (val >> 8) & 0x3FU;
|
||||||
|
mul += 2;
|
||||||
|
div = val & 0x07U;
|
||||||
|
return (parent_rate * mul) >> div;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (pll->id == 2) {
|
||||||
|
u8 mul;
|
||||||
|
|
||||||
|
mul = (val >> 24) & 0x3FU;
|
||||||
|
mul += 2;
|
||||||
|
return (parent_rate * mul);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Unknown PLL */
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static const struct clk_ops pll_clk_ops = {
|
||||||
|
.enable = pll_clk_enable,
|
||||||
|
.disable = pll_clk_disable,
|
||||||
|
.is_enabled = pll_clk_is_enabled,
|
||||||
|
.recalc_rate = pll_clk_recalc_rate,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct clk * __init
|
||||||
|
pll_clk_register(struct device *dev, const char *name,
|
||||||
|
const char *parent_name, u32 id)
|
||||||
|
{
|
||||||
|
struct clk *clk;
|
||||||
|
struct clk_pll *pll;
|
||||||
|
struct clk_init_data init;
|
||||||
|
|
||||||
|
if (id != 1 && id != 2) {
|
||||||
|
pr_err("%s: the Nomadik has only PLL 1 & 2\n", __func__);
|
||||||
|
return ERR_PTR(-EINVAL);
|
||||||
|
}
|
||||||
|
|
||||||
|
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||||
|
if (!pll) {
|
||||||
|
pr_err("%s: could not allocate PLL clk\n", __func__);
|
||||||
|
return ERR_PTR(-ENOMEM);
|
||||||
|
}
|
||||||
|
|
||||||
|
init.name = name;
|
||||||
|
init.ops = &pll_clk_ops;
|
||||||
|
init.parent_names = (parent_name ? &parent_name : NULL);
|
||||||
|
init.num_parents = (parent_name ? 1 : 0);
|
||||||
|
pll->hw.init = &init;
|
||||||
|
pll->id = id;
|
||||||
|
|
||||||
|
pr_debug("register PLL1 clock \"%s\"\n", name);
|
||||||
|
|
||||||
|
clk = clk_register(dev, &pll->hw);
|
||||||
|
if (IS_ERR(clk))
|
||||||
|
kfree(pll);
|
||||||
|
|
||||||
|
return clk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The Nomadik SRC clocks are gated, but not in the sense that
|
||||||
|
* you read-modify-write a register. Instead there are separate
|
||||||
|
* clock enable and clock disable registers. Writing a '1' bit in
|
||||||
|
* the enable register for a certain clock ungates that clock without
|
||||||
|
* affecting the other clocks. The disable register works the opposite
|
||||||
|
* way.
|
||||||
|
*/
|
||||||
|
|
||||||
|
static int src_clk_enable(struct clk_hw *hw)
|
||||||
|
{
|
||||||
|
struct clk_src *sclk = to_src(hw);
|
||||||
|
u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0;
|
||||||
|
u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
|
||||||
|
|
||||||
|
writel(sclk->clkbit, src_base + enreg);
|
||||||
|
/* spin until enabled */
|
||||||
|
while (!(readl(src_base + sreg) & sclk->clkbit))
|
||||||
|
cpu_relax();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void src_clk_disable(struct clk_hw *hw)
|
||||||
|
{
|
||||||
|
struct clk_src *sclk = to_src(hw);
|
||||||
|
u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0;
|
||||||
|
u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
|
||||||
|
|
||||||
|
writel(sclk->clkbit, src_base + disreg);
|
||||||
|
/* spin until disabled */
|
||||||
|
while (readl(src_base + sreg) & sclk->clkbit)
|
||||||
|
cpu_relax();
|
||||||
|
}
|
||||||
|
|
||||||
|
static int src_clk_is_enabled(struct clk_hw *hw)
|
||||||
|
{
|
||||||
|
struct clk_src *sclk = to_src(hw);
|
||||||
|
u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
|
||||||
|
u32 val = readl(src_base + sreg);
|
||||||
|
|
||||||
|
return !!(val & sclk->clkbit);
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned long
|
||||||
|
src_clk_recalc_rate(struct clk_hw *hw,
|
||||||
|
unsigned long parent_rate)
|
||||||
|
{
|
||||||
|
return parent_rate;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct clk_ops src_clk_ops = {
|
||||||
|
.enable = src_clk_enable,
|
||||||
|
.disable = src_clk_disable,
|
||||||
|
.is_enabled = src_clk_is_enabled,
|
||||||
|
.recalc_rate = src_clk_recalc_rate,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct clk * __init
|
||||||
|
src_clk_register(struct device *dev, const char *name,
|
||||||
|
const char *parent_name, u8 id)
|
||||||
|
{
|
||||||
|
struct clk *clk;
|
||||||
|
struct clk_src *sclk;
|
||||||
|
struct clk_init_data init;
|
||||||
|
|
||||||
|
sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
|
||||||
|
if (!sclk) {
|
||||||
|
pr_err("could not allocate SRC clock %s\n",
|
||||||
|
name);
|
||||||
|
return ERR_PTR(-ENOMEM);
|
||||||
|
}
|
||||||
|
init.name = name;
|
||||||
|
init.ops = &src_clk_ops;
|
||||||
|
/* Do not force-disable the static SDRAM controller */
|
||||||
|
if (id == 2)
|
||||||
|
init.flags = CLK_IGNORE_UNUSED;
|
||||||
|
else
|
||||||
|
init.flags = 0;
|
||||||
|
init.parent_names = (parent_name ? &parent_name : NULL);
|
||||||
|
init.num_parents = (parent_name ? 1 : 0);
|
||||||
|
sclk->hw.init = &init;
|
||||||
|
sclk->id = id;
|
||||||
|
sclk->group1 = (id > 31);
|
||||||
|
sclk->clkbit = BIT(id & 0x1f);
|
||||||
|
|
||||||
|
pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n",
|
||||||
|
name, id, sclk->group1, sclk->clkbit);
|
||||||
|
|
||||||
|
clk = clk_register(dev, &sclk->hw);
|
||||||
|
if (IS_ERR(clk))
|
||||||
|
kfree(sclk);
|
||||||
|
|
||||||
|
return clk;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_DEBUG_FS
|
||||||
|
|
||||||
|
static u32 src_pcksr0_boot;
|
||||||
|
static u32 src_pcksr1_boot;
|
||||||
|
|
||||||
|
static const char * const src_clk_names[] = {
|
||||||
|
"HCLKDMA0 ",
|
||||||
|
"HCLKSMC ",
|
||||||
|
"HCLKSDRAM ",
|
||||||
|
"HCLKDMA1 ",
|
||||||
|
"HCLKCLCD ",
|
||||||
|
"PCLKIRDA ",
|
||||||
|
"PCLKSSP ",
|
||||||
|
"PCLKUART0 ",
|
||||||
|
"PCLKSDI ",
|
||||||
|
"PCLKI2C0 ",
|
||||||
|
"PCLKI2C1 ",
|
||||||
|
"PCLKUART1 ",
|
||||||
|
"PCLMSP0 ",
|
||||||
|
"HCLKUSB ",
|
||||||
|
"HCLKDIF ",
|
||||||
|
"HCLKSAA ",
|
||||||
|
"HCLKSVA ",
|
||||||
|
"PCLKHSI ",
|
||||||
|
"PCLKXTI ",
|
||||||
|
"PCLKUART2 ",
|
||||||
|
"PCLKMSP1 ",
|
||||||
|
"PCLKMSP2 ",
|
||||||
|
"PCLKOWM ",
|
||||||
|
"HCLKHPI ",
|
||||||
|
"PCLKSKE ",
|
||||||
|
"PCLKHSEM ",
|
||||||
|
"HCLK3D ",
|
||||||
|
"HCLKHASH ",
|
||||||
|
"HCLKCRYP ",
|
||||||
|
"PCLKMSHC ",
|
||||||
|
"HCLKUSBM ",
|
||||||
|
"HCLKRNG ",
|
||||||
|
"RESERVED ",
|
||||||
|
"RESERVED ",
|
||||||
|
"RESERVED ",
|
||||||
|
"RESERVED ",
|
||||||
|
"CLDCLK ",
|
||||||
|
"IRDACLK ",
|
||||||
|
"SSPICLK ",
|
||||||
|
"UART0CLK ",
|
||||||
|
"SDICLK ",
|
||||||
|
"I2C0CLK ",
|
||||||
|
"I2C1CLK ",
|
||||||
|
"UART1CLK ",
|
||||||
|
"MSPCLK0 ",
|
||||||
|
"USBCLK ",
|
||||||
|
"DIFCLK ",
|
||||||
|
"IPI2CCLK ",
|
||||||
|
"IPBMCCLK ",
|
||||||
|
"HSICLKRX ",
|
||||||
|
"HSICLKTX ",
|
||||||
|
"UART2CLK ",
|
||||||
|
"MSPCLK1 ",
|
||||||
|
"MSPCLK2 ",
|
||||||
|
"OWMCLK ",
|
||||||
|
"RESERVED ",
|
||||||
|
"SKECLK ",
|
||||||
|
"RESERVED ",
|
||||||
|
"3DCLK ",
|
||||||
|
"PCLKMSP3 ",
|
||||||
|
"MSPCLK3 ",
|
||||||
|
"MSHCCLK ",
|
||||||
|
"USBMCLK ",
|
||||||
|
"RNGCCLK ",
|
||||||
|
};
|
||||||
|
|
||||||
|
static int nomadik_src_clk_show(struct seq_file *s, void *what)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
u32 src_pcksr0 = readl(src_base + SRC_PCKSR0);
|
||||||
|
u32 src_pcksr1 = readl(src_base + SRC_PCKSR1);
|
||||||
|
u32 src_pckensr0 = readl(src_base + SRC_PCKENSR0);
|
||||||
|
u32 src_pckensr1 = readl(src_base + SRC_PCKENSR1);
|
||||||
|
|
||||||
|
seq_printf(s, "Clock: Boot: Now: Request: ASKED:\n");
|
||||||
|
for (i = 0; i < ARRAY_SIZE(src_clk_names); i++) {
|
||||||
|
u32 pcksrb = (i < 0x20) ? src_pcksr0_boot : src_pcksr1_boot;
|
||||||
|
u32 pcksr = (i < 0x20) ? src_pcksr0 : src_pcksr1;
|
||||||
|
u32 pckreq = (i < 0x20) ? src_pckensr0 : src_pckensr1;
|
||||||
|
u32 mask = BIT(i & 0x1f);
|
||||||
|
|
||||||
|
seq_printf(s, "%s %s %s %s\n",
|
||||||
|
src_clk_names[i],
|
||||||
|
(pcksrb & mask) ? "on " : "off",
|
||||||
|
(pcksr & mask) ? "on " : "off",
|
||||||
|
(pckreq & mask) ? "on " : "off");
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int nomadik_src_clk_open(struct inode *inode, struct file *file)
|
||||||
|
{
|
||||||
|
return single_open(file, nomadik_src_clk_show, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct file_operations nomadik_src_clk_debugfs_ops = {
|
||||||
|
.open = nomadik_src_clk_open,
|
||||||
|
.read = seq_read,
|
||||||
|
.llseek = seq_lseek,
|
||||||
|
.release = single_release,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init nomadik_src_clk_init_debugfs(void)
|
||||||
|
{
|
||||||
|
src_pcksr0_boot = readl(src_base + SRC_PCKSR0);
|
||||||
|
src_pcksr1_boot = readl(src_base + SRC_PCKSR1);
|
||||||
|
debugfs_create_file("nomadik-src-clk", S_IFREG | S_IRUGO,
|
||||||
|
NULL, NULL, &nomadik_src_clk_debugfs_ops);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
module_init(nomadik_src_clk_init_debugfs);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static void __init of_nomadik_pll_setup(struct device_node *np)
|
||||||
|
{
|
||||||
|
struct clk *clk = ERR_PTR(-EINVAL);
|
||||||
|
const char *clk_name = np->name;
|
||||||
|
const char *parent_name;
|
||||||
|
u32 pll_id;
|
||||||
|
|
||||||
|
if (of_property_read_u32(np, "pll-id", &pll_id)) {
|
||||||
|
pr_err("%s: PLL \"%s\" missing pll-id property\n",
|
||||||
|
__func__, clk_name);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
parent_name = of_clk_get_parent_name(np, 0);
|
||||||
|
clk = pll_clk_register(NULL, clk_name, parent_name, pll_id);
|
||||||
|
if (!IS_ERR(clk))
|
||||||
|
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __init of_nomadik_hclk_setup(struct device_node *np)
|
||||||
|
{
|
||||||
|
struct clk *clk = ERR_PTR(-EINVAL);
|
||||||
|
const char *clk_name = np->name;
|
||||||
|
const char *parent_name;
|
||||||
|
|
||||||
|
parent_name = of_clk_get_parent_name(np, 0);
|
||||||
|
/*
|
||||||
|
* The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4.
|
||||||
|
*/
|
||||||
|
clk = clk_register_divider(NULL, clk_name, parent_name,
|
||||||
|
0, src_base + SRC_CR,
|
||||||
|
13, 2,
|
||||||
|
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
|
||||||
|
&src_lock);
|
||||||
|
if (!IS_ERR(clk))
|
||||||
|
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __init of_nomadik_src_clk_setup(struct device_node *np)
|
||||||
|
{
|
||||||
|
struct clk *clk = ERR_PTR(-EINVAL);
|
||||||
|
const char *clk_name = np->name;
|
||||||
|
const char *parent_name;
|
||||||
|
u32 clk_id;
|
||||||
|
|
||||||
|
if (of_property_read_u32(np, "clock-id", &clk_id)) {
|
||||||
|
pr_err("%s: SRC clock \"%s\" missing clock-id property\n",
|
||||||
|
__func__, clk_name);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
parent_name = of_clk_get_parent_name(np, 0);
|
||||||
|
clk = src_clk_register(NULL, clk_name, parent_name, clk_id);
|
||||||
|
if (!IS_ERR(clk))
|
||||||
|
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const __initconst struct of_device_id nomadik_src_match[] = {
|
||||||
|
{ .compatible = "stericsson,nomadik-src" },
|
||||||
{ /* sentinel */ }
|
{ /* sentinel */ }
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const __initconst struct of_device_id nomadik_src_clk_match[] = {
|
||||||
|
{
|
||||||
|
.compatible = "fixed-clock",
|
||||||
|
.data = of_fixed_clk_setup,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.compatible = "fixed-factor-clock",
|
||||||
|
.data = of_fixed_factor_clk_setup,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.compatible = "st,nomadik-pll-clock",
|
||||||
|
.data = of_nomadik_pll_setup,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.compatible = "st,nomadik-hclk-clock",
|
||||||
|
.data = of_nomadik_hclk_setup,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.compatible = "st,nomadik-src-clock",
|
||||||
|
.data = of_nomadik_src_clk_setup,
|
||||||
|
},
|
||||||
|
{ /* sentinel */ }
|
||||||
|
};
|
||||||
|
|
||||||
|
static int nomadik_clk_reboot_handler(struct notifier_block *this,
|
||||||
|
unsigned long code,
|
||||||
|
void *unused)
|
||||||
|
{
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
/* The main chrystal need to be enabled for reboot to work */
|
||||||
|
val = readl(src_base + SRC_XTALCR);
|
||||||
|
val &= ~SRC_XTALCR_MXTALOVER;
|
||||||
|
val |= SRC_XTALCR_MXTALEN;
|
||||||
|
pr_crit("force-enabling MXTALO\n");
|
||||||
|
writel(val, src_base + SRC_XTALCR);
|
||||||
|
return NOTIFY_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct notifier_block nomadik_clk_reboot_notifier = {
|
||||||
|
.notifier_call = nomadik_clk_reboot_handler,
|
||||||
|
};
|
||||||
|
|
||||||
void __init nomadik_clk_init(void)
|
void __init nomadik_clk_init(void)
|
||||||
{
|
{
|
||||||
of_clk_init(cpu8815_clk_match);
|
struct device_node *np;
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
np = of_find_matching_node(NULL, nomadik_src_match);
|
||||||
|
if (!np) {
|
||||||
|
pr_crit("no matching node for SRC, aborting clock init\n");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
src_base = of_iomap(np, 0);
|
||||||
|
if (!src_base) {
|
||||||
|
pr_err("%s: must have src parent node with REGS (%s)\n",
|
||||||
|
__func__, np->name);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
val = readl(src_base + SRC_XTALCR);
|
||||||
|
pr_info("SXTALO is %s\n",
|
||||||
|
(val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled");
|
||||||
|
pr_info("MXTAL is %s\n",
|
||||||
|
(val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled");
|
||||||
|
if (of_property_read_bool(np, "disable-sxtalo")) {
|
||||||
|
/* The machine uses an external oscillator circuit */
|
||||||
|
val |= SRC_XTALCR_SXTALDIS;
|
||||||
|
pr_info("disabling SXTALO\n");
|
||||||
|
}
|
||||||
|
if (of_property_read_bool(np, "disable-mxtalo")) {
|
||||||
|
/* Disable this too: also run by external oscillator */
|
||||||
|
val |= SRC_XTALCR_MXTALOVER;
|
||||||
|
val &= ~SRC_XTALCR_MXTALEN;
|
||||||
|
pr_info("disabling MXTALO\n");
|
||||||
|
}
|
||||||
|
writel(val, src_base + SRC_XTALCR);
|
||||||
|
register_reboot_notifier(&nomadik_clk_reboot_notifier);
|
||||||
|
|
||||||
|
of_clk_init(nomadik_src_clk_match);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -2104,7 +2104,7 @@ static struct pinctrl_desc nmk_pinctrl_desc = {
|
||||||
|
|
||||||
static const struct of_device_id nmk_pinctrl_match[] = {
|
static const struct of_device_id nmk_pinctrl_match[] = {
|
||||||
{
|
{
|
||||||
.compatible = "stericsson,nmk-pinctrl-stn8815",
|
.compatible = "stericsson,stn8815-pinctrl",
|
||||||
.data = (void *)PINCTRL_NMK_STN8815,
|
.data = (void *)PINCTRL_NMK_STN8815,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue