Allwinner DT patches for 3.15, take 1:
- Add SPI controllers for all the SoCs - Add various missing aliases - Add USB clocks nodes - Addition of the GMAC support - Introduction of the pcDuino board - A few DT cleanup patches: change of compatibles, -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJTFFhJAAoJEBx+YmzsjxAgFfsQALAcX5Vyw6Qi7vOQEipsY/Cv spaokviWKhanViYNDxMt0Q03rHUNIYbGD9bQA6V+dw5k4LFX1ww3BPQhlQm4kAw/ MjGTdD+Mgg2cwdGw3YvT3hot2iYgy3HOxEdA9UPX1SKPAVmyoKk5SasZr7Lb+6zk N2Ezpz8+erE8WVrg/2SoP91LoU13vJX0Z9hsiBUCjRtYS75Zs7qF6hf03oqYg+EK j0vp3f1NdVIMItS/4UlBz4lqwNWJRQb2Q1JX0BKI9ITBGv7RlNcJoe3A/qKpqtAf jb1cvld2orj9a677PDvQbYfarUcWpJEckp5ypTl33i4amzQbCYhZRY+kmltKQmsY iaJa+OYHCRgZgzE7kBll3WG/69BoV+9g56bqRD0+kudXZoD2JIEb6sDYjBiGqNh/ vwSvdDR1Pblw9Af9fGe8OK5E0/RJQWzT0PQLZnPDfPDLk5LxuQsytYhujrHZExte eYIUm9M8g9f5UAA70bSO2HjNmVUdS2kmFp09GaObOfqLZBp5vHCxQpAeY20tyQ1z 0bcrqK+RTN8EvyjWuGyr8sMReZclKsOi/KrO6kgvVtTUMH1tt7v4OxxrZv99sdQv tA4wk9R4gs+owKh/DTkSMj91vLgzk/e+DoNhLp1oAHlU/qX2/AOSfzKTnhUh4cML zFsZzST0/kSXs3lU2UPN =mXsD -----END PGP SIGNATURE----- Merge tag 'sunxi-dt-for-3.15' of https://github.com/mripard/linux into next/dt Allwinner DT patches for 3.15, take 1 from Maxime Ripard: - Add SPI controllers for all the SoCs - Add various missing aliases - Add USB clocks nodes - Addition of the GMAC support - Introduction of the pcDuino board - A few DT cleanup patches: change of compatibles, * tag 'sunxi-dt-for-3.15' of https://github.com/mripard/linux: (33 commits) ARM: sun6i: dt: Fix mod0 compatible ARM: dts: sun7i: Enable the SPI controllers of the A20-olinuxino-micro ARM: dt: sun7i: Add SPI muxing options ARM: dt: sun5i: Add A13 SPI controller nodes ARM: dt: sun5i: Add A10s SPI controller nodes ARM: dt: sun4i: Add A10 SPI controller nodes ARM: dt: sun7i: Add A20 SPI controller nodes ARM: sun4i: dt: Remove grouping + simple-bus compatible for regulators ARM: sunxi: dt: Convert to the new clock compatibles ARM: sun7i: add arch timer node ARM: sun7i: dt: Add bindings for USB clocks ARM: sun5i: dt: Add bindings for USB clocks ARM: sun4i: dt: Add bindings for USB clocks ARM: dts: sun7i: Add ethernet alias for GMAC ARM: dts: sun7i: a20-olinuxino-micro: Enable GMAC instead of EMAC ARM: dts: sun7i: cubieboard2: Enable GMAC instead of EMAC ARM: dts: sun7i: cubietruck: Enable the GMAC ARM: dts: sun7i: Add pin muxing options for the GMAC ARM: dts: sun7i: Add GMAC controller node to sun7i DTSI ARM: dts: sun7i: Add GMAC clock node to sun7i DTSI ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
1809136044
12 changed files with 711 additions and 210 deletions
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@ -322,6 +322,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
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sun4i-a10-cubieboard.dtb \
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sun4i-a10-mini-xplus.dtb \
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sun4i-a10-hackberry.dtb \
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sun4i-a10-pcduino.dtb \
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sun5i-a10s-olinuxino-micro.dtb \
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sun5i-a13-olinuxino.dtb \
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sun5i-a13-olinuxino-micro.dtb \
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@ -80,18 +80,14 @@
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};
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};
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regulators {
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compatible = "simple-bus";
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reg_emac_3v3: emac-3v3 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&emac_power_pin_a1000>;
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regulator-name = "emac-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&pio 7 15 0>;
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};
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reg_emac_3v3: emac-3v3 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&emac_power_pin_a1000>;
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regulator-name = "emac-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&pio 7 15 0>;
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};
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};
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@ -54,16 +54,12 @@
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};
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};
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regulators {
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compatible = "simple-bus";
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reg_emac_3v3: emac-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "emac-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&pio 7 19 0>;
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};
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reg_emac_3v3: emac-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "emac-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&pio 7 19 0>;
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};
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};
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48
arch/arm/boot/dts/sun4i-a10-pcduino.dts
Normal file
48
arch/arm/boot/dts/sun4i-a10-pcduino.dts
Normal file
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@ -0,0 +1,48 @@
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/*
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* Copyright 2014 Zoltan HERPAI
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* Zoltan HERPAI <wigyori@uid0.hu>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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/include/ "sun4i-a10.dtsi"
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/ {
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model = "LinkSprite pcDuino";
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compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10";
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soc@01c00000 {
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emac: ethernet@01c0b000 {
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pinctrl-names = "default";
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pinctrl-0 = <&emac_pins_a>;
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phy = <&phy1>;
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status = "okay";
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};
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mdio@01c0b080 {
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status = "okay";
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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uart0: serial@01c28000 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins_a>;
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status = "okay";
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};
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i2c0: i2c@01c2ac00 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins_a>;
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status = "okay";
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};
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};
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};
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@ -19,6 +19,12 @@
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ethernet0 = &emac;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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serial6 = &uart6;
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serial7 = &uart7;
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};
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cpus {
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@ -52,44 +58,48 @@
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clock-frequency = <0>;
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};
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osc24M: osc24M@01c20050 {
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osc24M: clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-osc-clk";
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compatible = "allwinner,sun4i-a10-osc-clk";
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reg = <0x01c20050 0x4>;
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k {
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osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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pll1: pll1@01c20000 {
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pll1: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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compatible = "allwinner,sun4i-a10-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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};
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pll4: pll4@01c20018 {
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pll4: clk@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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compatible = "allwinner,sun4i-a10-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll4";
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};
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pll5: pll5@01c20020 {
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pll5: clk@01c20020 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll5-clk";
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compatible = "allwinner,sun4i-a10-pll5-clk";
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reg = <0x01c20020 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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pll6: pll6@01c20028 {
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pll6: clk@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll6-clk";
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compatible = "allwinner,sun4i-a10-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6_sata", "pll6_other", "pll6";
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@ -98,21 +108,23 @@
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-cpu-clk";
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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clock-output-names = "cpu";
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};
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axi: axi@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-axi-clk";
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compatible = "allwinner,sun4i-a10-axi-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&cpu>;
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clock-output-names = "axi";
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};
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axi_gates: axi_gates@01c2005c {
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axi_gates: clk@01c2005c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-axi-gates-clk";
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compatible = "allwinner,sun4i-a10-axi-gates-clk";
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reg = <0x01c2005c 0x4>;
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clocks = <&axi>;
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clock-output-names = "axi_dram";
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@ -120,14 +132,15 @@
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ahb: ahb@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-ahb-clk";
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compatible = "allwinner,sun4i-a10-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&axi>;
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clock-output-names = "ahb";
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};
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ahb_gates: ahb_gates@01c20060 {
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ahb_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-ahb-gates-clk";
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compatible = "allwinner,sun4i-a10-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-output-names = "ahb_usb0", "ahb_ehci0",
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@ -145,14 +158,15 @@
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apb0: apb0@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb0-clk";
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compatible = "allwinner,sun4i-a10-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb>;
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clock-output-names = "apb0";
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};
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apb0_gates: apb0_gates@01c20068 {
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apb0_gates: clk@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-apb0-gates-clk";
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compatible = "allwinner,sun4i-a10-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-output-names = "apb0_codec", "apb0_spdif",
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@ -162,21 +176,23 @@
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apb1_mux: apb1_mux@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-mux-clk";
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compatible = "allwinner,sun4i-a10-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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clock-output-names = "apb1_mux";
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};
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apb1: apb1@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-clk";
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compatible = "allwinner,sun4i-a10-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&apb1_mux>;
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clock-output-names = "apb1";
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};
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apb1_gates: apb1_gates@01c2006c {
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apb1_gates: clk@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-apb1-gates-clk";
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compatible = "allwinner,sun4i-a10-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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@ -189,7 +205,7 @@
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nand_clk: clk@01c20080 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20080 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "nand";
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@ -197,7 +213,7 @@
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ms_clk: clk@01c20084 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20084 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ms";
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@ -205,7 +221,7 @@
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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|
@ -213,7 +229,7 @@
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|||
|
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mmc1_clk: clk@01c2008c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c2008c 0x4>;
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||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc1";
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||||
|
|
@ -221,7 +237,7 @@
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|||
|
||||
mmc2_clk: clk@01c20090 {
|
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#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20090 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc2";
|
||||
|
|
@ -229,7 +245,7 @@
|
|||
|
||||
mmc3_clk: clk@01c20094 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20094 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc3";
|
||||
|
|
@ -237,7 +253,7 @@
|
|||
|
||||
ts_clk: clk@01c20098 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20098 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ts";
|
||||
|
|
@ -245,7 +261,7 @@
|
|||
|
||||
ss_clk: clk@01c2009c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c2009c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ss";
|
||||
|
|
@ -253,7 +269,7 @@
|
|||
|
||||
spi0_clk: clk@01c200a0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi0";
|
||||
|
|
@ -261,7 +277,7 @@
|
|||
|
||||
spi1_clk: clk@01c200a4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi1";
|
||||
|
|
@ -269,7 +285,7 @@
|
|||
|
||||
spi2_clk: clk@01c200a8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a8 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi2";
|
||||
|
|
@ -277,7 +293,7 @@
|
|||
|
||||
pata_clk: clk@01c200ac {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200ac 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "pata";
|
||||
|
|
@ -285,7 +301,7 @@
|
|||
|
||||
ir0_clk: clk@01c200b0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200b0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ir0";
|
||||
|
|
@ -293,15 +309,24 @@
|
|||
|
||||
ir1_clk: clk@01c200b4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200b4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ir1";
|
||||
};
|
||||
|
||||
usb_clk: clk@01c200cc {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-usb-clk";
|
||||
reg = <0x01c200cc 0x4>;
|
||||
clocks = <&pll6 1>;
|
||||
clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
|
||||
};
|
||||
|
||||
spi3_clk: clk@01c200d4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200d4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi3";
|
||||
|
|
@ -314,6 +339,28 @@
|
|||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
spi0: spi@01c05000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c05000 0x1000>;
|
||||
interrupts = <10>;
|
||||
clocks = <&ahb_gates 20>, <&spi0_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1: spi@01c06000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c06000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&ahb_gates 21>, <&spi1_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emac: ethernet@01c0b000 {
|
||||
compatible = "allwinner,sun4i-a10-emac";
|
||||
reg = <0x01c0b000 0x1000>;
|
||||
|
|
@ -330,6 +377,28 @@
|
|||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi2: spi@01c17000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c17000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&ahb_gates 22>, <&spi2_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi3: spi@01c1f000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c1f000 0x1000>;
|
||||
interrupts = <50>;
|
||||
clocks = <&ahb_gates 23>, <&spi3_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@01c20400 {
|
||||
compatible = "allwinner,sun4i-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
|
|
|
|||
|
|
@ -18,6 +18,10 @@
|
|||
|
||||
aliases {
|
||||
ethernet0 = &emac;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -47,44 +51,48 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc24M: osc24M@01c20050 {
|
||||
osc24M: clk@01c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-osc-clk";
|
||||
compatible = "allwinner,sun4i-a10-osc-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc24M";
|
||||
};
|
||||
|
||||
osc32k: osc32k {
|
||||
osc32k: clk@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc32k";
|
||||
};
|
||||
|
||||
pll1: pll1@01c20000 {
|
||||
pll1: clk@01c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll1";
|
||||
};
|
||||
|
||||
pll4: pll4@01c20018 {
|
||||
pll4: clk@01c20018 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll1-clk";
|
||||
reg = <0x01c20018 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll4";
|
||||
};
|
||||
|
||||
pll5: pll5@01c20020 {
|
||||
pll5: clk@01c20020 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-pll5-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll5-clk";
|
||||
reg = <0x01c20020 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll5_ddr", "pll5_other";
|
||||
};
|
||||
|
||||
pll6: pll6@01c20028 {
|
||||
pll6: clk@01c20028 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-pll6-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll6-clk";
|
||||
reg = <0x01c20028 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll6_sata", "pll6_other", "pll6";
|
||||
|
|
@ -93,21 +101,23 @@
|
|||
/* dummy is 200M */
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-cpu-clk";
|
||||
compatible = "allwinner,sun4i-a10-cpu-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
|
||||
clock-output-names = "cpu";
|
||||
};
|
||||
|
||||
axi: axi@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-axi-clk";
|
||||
compatible = "allwinner,sun4i-a10-axi-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&cpu>;
|
||||
clock-output-names = "axi";
|
||||
};
|
||||
|
||||
axi_gates: axi_gates@01c2005c {
|
||||
axi_gates: clk@01c2005c {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-axi-gates-clk";
|
||||
compatible = "allwinner,sun4i-a10-axi-gates-clk";
|
||||
reg = <0x01c2005c 0x4>;
|
||||
clocks = <&axi>;
|
||||
clock-output-names = "axi_dram";
|
||||
|
|
@ -115,12 +125,13 @@
|
|||
|
||||
ahb: ahb@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-ahb-clk";
|
||||
compatible = "allwinner,sun4i-a10-ahb-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&axi>;
|
||||
clock-output-names = "ahb";
|
||||
};
|
||||
|
||||
ahb_gates: ahb_gates@01c20060 {
|
||||
ahb_gates: clk@01c20060 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
|
||||
reg = <0x01c20060 0x8>;
|
||||
|
|
@ -136,12 +147,13 @@
|
|||
|
||||
apb0: apb0@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb0-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb0-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&ahb>;
|
||||
clock-output-names = "apb0";
|
||||
};
|
||||
|
||||
apb0_gates: apb0_gates@01c20068 {
|
||||
apb0_gates: clk@01c20068 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
|
||||
reg = <0x01c20068 0x4>;
|
||||
|
|
@ -152,19 +164,21 @@
|
|||
|
||||
apb1_mux: apb1_mux@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb1-mux-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1_mux";
|
||||
};
|
||||
|
||||
apb1: apb1@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb1-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb1-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&apb1_mux>;
|
||||
clock-output-names = "apb1";
|
||||
};
|
||||
|
||||
apb1_gates: apb1_gates@01c2006c {
|
||||
apb1_gates: clk@01c2006c {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
|
||||
reg = <0x01c2006c 0x4>;
|
||||
|
|
@ -176,7 +190,7 @@
|
|||
|
||||
nand_clk: clk@01c20080 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20080 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "nand";
|
||||
|
|
@ -184,7 +198,7 @@
|
|||
|
||||
ms_clk: clk@01c20084 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20084 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ms";
|
||||
|
|
@ -192,7 +206,7 @@
|
|||
|
||||
mmc0_clk: clk@01c20088 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20088 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc0";
|
||||
|
|
@ -200,7 +214,7 @@
|
|||
|
||||
mmc1_clk: clk@01c2008c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c2008c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc1";
|
||||
|
|
@ -208,7 +222,7 @@
|
|||
|
||||
mmc2_clk: clk@01c20090 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20090 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc2";
|
||||
|
|
@ -216,7 +230,7 @@
|
|||
|
||||
ts_clk: clk@01c20098 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20098 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ts";
|
||||
|
|
@ -224,7 +238,7 @@
|
|||
|
||||
ss_clk: clk@01c2009c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c2009c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ss";
|
||||
|
|
@ -232,7 +246,7 @@
|
|||
|
||||
spi0_clk: clk@01c200a0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi0";
|
||||
|
|
@ -240,7 +254,7 @@
|
|||
|
||||
spi1_clk: clk@01c200a4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi1";
|
||||
|
|
@ -248,7 +262,7 @@
|
|||
|
||||
spi2_clk: clk@01c200a8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a8 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi2";
|
||||
|
|
@ -256,15 +270,24 @@
|
|||
|
||||
ir0_clk: clk@01c200b0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200b0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ir0";
|
||||
};
|
||||
|
||||
usb_clk: clk@01c200cc {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun5i-a13-usb-clk";
|
||||
reg = <0x01c200cc 0x4>;
|
||||
clocks = <&pll6 1>;
|
||||
clock-output-names = "usb_ohci0", "usb_phy";
|
||||
};
|
||||
|
||||
mbus_clk: clk@01c2015c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c2015c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mbus";
|
||||
|
|
@ -277,6 +300,28 @@
|
|||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
spi0: spi@01c05000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c05000 0x1000>;
|
||||
interrupts = <10>;
|
||||
clocks = <&ahb_gates 20>, <&spi0_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1: spi@01c06000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c06000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&ahb_gates 21>, <&spi1_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emac: ethernet@01c0b000 {
|
||||
compatible = "allwinner,sun4i-a10-emac";
|
||||
reg = <0x01c0b000 0x1000>;
|
||||
|
|
@ -293,6 +338,17 @@
|
|||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi2: spi@01c17000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c17000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&ahb_gates 22>, <&spi2_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@01c20400 {
|
||||
compatible = "allwinner,sun4i-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
|
|
|
|||
|
|
@ -16,6 +16,11 @@
|
|||
/ {
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -47,44 +52,48 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc24M: osc24M@01c20050 {
|
||||
osc24M: clk@01c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-osc-clk";
|
||||
compatible = "allwinner,sun4i-a10-osc-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc24M";
|
||||
};
|
||||
|
||||
osc32k: osc32k {
|
||||
osc32k: clk@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc32k";
|
||||
};
|
||||
|
||||
pll1: pll1@01c20000 {
|
||||
pll1: clk@01c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll1";
|
||||
};
|
||||
|
||||
pll4: pll4@01c20018 {
|
||||
pll4: clk@01c20018 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll1-clk";
|
||||
reg = <0x01c20018 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll4";
|
||||
};
|
||||
|
||||
pll5: pll5@01c20020 {
|
||||
pll5: clk@01c20020 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-pll5-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll5-clk";
|
||||
reg = <0x01c20020 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll5_ddr", "pll5_other";
|
||||
};
|
||||
|
||||
pll6: pll6@01c20028 {
|
||||
pll6: clk@01c20028 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-pll6-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll6-clk";
|
||||
reg = <0x01c20028 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll6_sata", "pll6_other", "pll6";
|
||||
|
|
@ -93,21 +102,23 @@
|
|||
/* dummy is 200M */
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-cpu-clk";
|
||||
compatible = "allwinner,sun4i-a10-cpu-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
|
||||
clock-output-names = "cpu";
|
||||
};
|
||||
|
||||
axi: axi@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-axi-clk";
|
||||
compatible = "allwinner,sun4i-a10-axi-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&cpu>;
|
||||
clock-output-names = "axi";
|
||||
};
|
||||
|
||||
axi_gates: axi_gates@01c2005c {
|
||||
axi_gates: clk@01c2005c {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-axi-gates-clk";
|
||||
compatible = "allwinner,sun4i-a10-axi-gates-clk";
|
||||
reg = <0x01c2005c 0x4>;
|
||||
clocks = <&axi>;
|
||||
clock-output-names = "axi_dram";
|
||||
|
|
@ -115,12 +126,13 @@
|
|||
|
||||
ahb: ahb@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-ahb-clk";
|
||||
compatible = "allwinner,sun4i-a10-ahb-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&axi>;
|
||||
clock-output-names = "ahb";
|
||||
};
|
||||
|
||||
ahb_gates: ahb_gates@01c20060 {
|
||||
ahb_gates: clk@01c20060 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun5i-a13-ahb-gates-clk";
|
||||
reg = <0x01c20060 0x8>;
|
||||
|
|
@ -135,12 +147,13 @@
|
|||
|
||||
apb0: apb0@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb0-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb0-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&ahb>;
|
||||
clock-output-names = "apb0";
|
||||
};
|
||||
|
||||
apb0_gates: apb0_gates@01c20068 {
|
||||
apb0_gates: clk@01c20068 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun5i-a13-apb0-gates-clk";
|
||||
reg = <0x01c20068 0x4>;
|
||||
|
|
@ -150,19 +163,21 @@
|
|||
|
||||
apb1_mux: apb1_mux@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb1-mux-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1_mux";
|
||||
};
|
||||
|
||||
apb1: apb1@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb1-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb1-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&apb1_mux>;
|
||||
clock-output-names = "apb1";
|
||||
};
|
||||
|
||||
apb1_gates: apb1_gates@01c2006c {
|
||||
apb1_gates: clk@01c2006c {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun5i-a13-apb1-gates-clk";
|
||||
reg = <0x01c2006c 0x4>;
|
||||
|
|
@ -173,7 +188,7 @@
|
|||
|
||||
nand_clk: clk@01c20080 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20080 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "nand";
|
||||
|
|
@ -181,7 +196,7 @@
|
|||
|
||||
ms_clk: clk@01c20084 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20084 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ms";
|
||||
|
|
@ -189,7 +204,7 @@
|
|||
|
||||
mmc0_clk: clk@01c20088 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20088 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc0";
|
||||
|
|
@ -197,7 +212,7 @@
|
|||
|
||||
mmc1_clk: clk@01c2008c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c2008c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc1";
|
||||
|
|
@ -205,7 +220,7 @@
|
|||
|
||||
mmc2_clk: clk@01c20090 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20090 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc2";
|
||||
|
|
@ -213,7 +228,7 @@
|
|||
|
||||
ts_clk: clk@01c20098 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20098 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ts";
|
||||
|
|
@ -221,7 +236,7 @@
|
|||
|
||||
ss_clk: clk@01c2009c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c2009c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ss";
|
||||
|
|
@ -229,7 +244,7 @@
|
|||
|
||||
spi0_clk: clk@01c200a0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi0";
|
||||
|
|
@ -237,7 +252,7 @@
|
|||
|
||||
spi1_clk: clk@01c200a4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi1";
|
||||
|
|
@ -245,7 +260,7 @@
|
|||
|
||||
spi2_clk: clk@01c200a8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a8 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi2";
|
||||
|
|
@ -253,15 +268,24 @@
|
|||
|
||||
ir0_clk: clk@01c200b0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200b0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ir0";
|
||||
};
|
||||
|
||||
usb_clk: clk@01c200cc {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun5i-a13-usb-clk";
|
||||
reg = <0x01c200cc 0x4>;
|
||||
clocks = <&pll6 1>;
|
||||
clock-output-names = "usb_ohci0", "usb_phy";
|
||||
};
|
||||
|
||||
mbus_clk: clk@01c2015c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c2015c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mbus";
|
||||
|
|
@ -274,6 +298,39 @@
|
|||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
spi0: spi@01c05000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c05000 0x1000>;
|
||||
interrupts = <10>;
|
||||
clocks = <&ahb_gates 20>, <&spi0_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1: spi@01c06000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c06000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&ahb_gates 21>, <&spi1_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi2: spi@01c17000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c17000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&ahb_gates 22>, <&spi2_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@01c20400 {
|
||||
compatible = "allwinner,sun4i-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
|
|
|
|||
|
|
@ -16,6 +16,16 @@
|
|||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
serial5 = &uart5;
|
||||
};
|
||||
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -60,34 +70,32 @@
|
|||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
osc32k: osc32k {
|
||||
osc32k: clk@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc32k";
|
||||
};
|
||||
|
||||
pll1: pll1@01c20000 {
|
||||
pll1: clk@01c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun6i-a31-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll1";
|
||||
};
|
||||
|
||||
/*
|
||||
* This is a dummy clock, to be used as placeholder on
|
||||
* other mux clocks when a specific parent clock is not
|
||||
* yet implemented. It should be dropped when the driver
|
||||
* is complete.
|
||||
*/
|
||||
pll6: pll6 {
|
||||
pll6: clk@01c20028 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
compatible = "allwinner,sun6i-a31-pll6-clk";
|
||||
reg = <0x01c20028 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll6";
|
||||
};
|
||||
|
||||
cpu: cpu@01c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-cpu-clk";
|
||||
compatible = "allwinner,sun4i-a10-cpu-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
|
||||
/*
|
||||
|
|
@ -97,13 +105,15 @@
|
|||
* Allwinner.
|
||||
*/
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
|
||||
clock-output-names = "cpu";
|
||||
};
|
||||
|
||||
axi: axi@01c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-axi-clk";
|
||||
compatible = "allwinner,sun4i-a10-axi-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
clocks = <&cpu>;
|
||||
clock-output-names = "axi";
|
||||
};
|
||||
|
||||
ahb1_mux: ahb1_mux@01c20054 {
|
||||
|
|
@ -111,16 +121,18 @@
|
|||
compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
|
||||
clock-output-names = "ahb1_mux";
|
||||
};
|
||||
|
||||
ahb1: ahb1@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-ahb-clk";
|
||||
compatible = "allwinner,sun4i-a10-ahb-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&ahb1_mux>;
|
||||
clock-output-names = "ahb1";
|
||||
};
|
||||
|
||||
ahb1_gates: ahb1_gates@01c20060 {
|
||||
ahb1_gates: clk@01c20060 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
|
||||
reg = <0x01c20060 0x8>;
|
||||
|
|
@ -143,12 +155,13 @@
|
|||
|
||||
apb1: apb1@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb0-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb0-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&ahb1>;
|
||||
clock-output-names = "apb1";
|
||||
};
|
||||
|
||||
apb1_gates: apb1_gates@01c20060 {
|
||||
apb1_gates: clk@01c20068 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-apb1-gates-clk";
|
||||
reg = <0x01c20068 0x4>;
|
||||
|
|
@ -160,9 +173,10 @@
|
|||
|
||||
apb2_mux: apb2_mux@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb1-mux-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
|
||||
clock-output-names = "apb2_mux";
|
||||
};
|
||||
|
||||
apb2: apb2@01c20058 {
|
||||
|
|
@ -170,9 +184,10 @@
|
|||
compatible = "allwinner,sun6i-a31-apb2-div-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&apb2_mux>;
|
||||
clock-output-names = "apb2";
|
||||
};
|
||||
|
||||
apb2_gates: apb2_gates@01c2006c {
|
||||
apb2_gates: clk@01c2006c {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-apb2-gates-clk";
|
||||
reg = <0x01c2006c 0x4>;
|
||||
|
|
@ -182,6 +197,38 @@
|
|||
"apb2_uart1", "apb2_uart2", "apb2_uart3",
|
||||
"apb2_uart4", "apb2_uart5";
|
||||
};
|
||||
|
||||
spi0_clk: clk@01c200a0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6>;
|
||||
clock-output-names = "spi0";
|
||||
};
|
||||
|
||||
spi1_clk: clk@01c200a4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6>;
|
||||
clock-output-names = "spi1";
|
||||
};
|
||||
|
||||
spi2_clk: clk@01c200a8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a8 0x4>;
|
||||
clocks = <&osc24M>, <&pll6>;
|
||||
clock-output-names = "spi2";
|
||||
};
|
||||
|
||||
spi3_clk: clk@01c200ac {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200ac 0x4>;
|
||||
clocks = <&osc24M>, <&pll6>;
|
||||
clock-output-names = "spi3";
|
||||
};
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
|
|
@ -312,6 +359,46 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@01c68000 {
|
||||
compatible = "allwinner,sun6i-a31-spi";
|
||||
reg = <0x01c68000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
clocks = <&ahb1_gates 20>, <&spi0_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
resets = <&ahb1_rst 20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@01c69000 {
|
||||
compatible = "allwinner,sun6i-a31-spi";
|
||||
reg = <0x01c69000 0x1000>;
|
||||
interrupts = <0 66 4>;
|
||||
clocks = <&ahb1_gates 21>, <&spi1_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
resets = <&ahb1_rst 21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@01c6a000 {
|
||||
compatible = "allwinner,sun6i-a31-spi";
|
||||
reg = <0x01c6a000 0x1000>;
|
||||
interrupts = <0 67 4>;
|
||||
clocks = <&ahb1_gates 22>, <&spi2_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
resets = <&ahb1_rst 22>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi3: spi@01c6b000 {
|
||||
compatible = "allwinner,sun6i-a31-spi";
|
||||
reg = <0x01c6b000 0x1000>;
|
||||
interrupts = <0 68 4>;
|
||||
clocks = <&ahb1_gates 23>, <&spi3_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
resets = <&ahb1_rst 23>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@01c81000 {
|
||||
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
||||
reg = <0x01c81000 0x1000>,
|
||||
|
|
|
|||
|
|
@ -19,21 +19,6 @@
|
|||
compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
|
||||
|
||||
soc@01c00000 {
|
||||
emac: ethernet@01c0b000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emac_pins_a>;
|
||||
phy = <&phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio@01c0b080 {
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@01c20800 {
|
||||
led_pins_cubieboard2: led_pins@0 {
|
||||
allwinner,pins = "PH20", "PH21";
|
||||
|
|
@ -60,6 +45,18 @@
|
|||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gmac: ethernet@01c50000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_pins_mii_a>;
|
||||
phy = <&phy1>;
|
||||
phy-mode = "mii";
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
|
|
|
|||
|
|
@ -51,6 +51,18 @@
|
|||
pinctrl-0 = <&i2c2_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gmac: ethernet@01c50000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_pins_rgmii_a>;
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
|
|
|
|||
|
|
@ -18,20 +18,22 @@
|
|||
model = "Olimex A20-Olinuxino Micro";
|
||||
compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi1;
|
||||
spi1 = &spi2;
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
emac: ethernet@01c0b000 {
|
||||
spi1: spi@01c06000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emac_pins_a>;
|
||||
phy = <&phy1>;
|
||||
pinctrl-0 = <&spi1_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio@01c0b080 {
|
||||
spi2: spi@01c17000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@01c20800 {
|
||||
|
|
@ -78,6 +80,18 @@
|
|||
pinctrl-0 = <&i2c2_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gmac: ethernet@01c50000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_pins_mii_a>;
|
||||
phy = <&phy1>;
|
||||
phy-mode = "mii";
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
|
|
|
|||
|
|
@ -17,7 +17,15 @@
|
|||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &emac;
|
||||
ethernet0 = &gmac;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
serial5 = &uart5;
|
||||
serial6 = &uart6;
|
||||
serial7 = &uart7;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -41,16 +49,25 @@
|
|||
reg = <0x40000000 0x80000000>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
osc24M: osc24M@01c20050 {
|
||||
osc24M: clk@01c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-osc-clk";
|
||||
compatible = "allwinner,sun4i-a10-osc-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc24M";
|
||||
};
|
||||
|
||||
osc32k: clk@0 {
|
||||
|
|
@ -60,31 +77,33 @@
|
|||
clock-output-names = "osc32k";
|
||||
};
|
||||
|
||||
pll1: pll1@01c20000 {
|
||||
pll1: clk@01c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll1";
|
||||
};
|
||||
|
||||
pll4: pll4@01c20018 {
|
||||
pll4: clk@01c20018 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll1-clk";
|
||||
reg = <0x01c20018 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll4";
|
||||
};
|
||||
|
||||
pll5: pll5@01c20020 {
|
||||
pll5: clk@01c20020 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-pll5-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll5-clk";
|
||||
reg = <0x01c20020 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll5_ddr", "pll5_other";
|
||||
};
|
||||
|
||||
pll6: pll6@01c20028 {
|
||||
pll6: clk@01c20028 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-pll6-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll6-clk";
|
||||
reg = <0x01c20028 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll6_sata", "pll6_other", "pll6";
|
||||
|
|
@ -92,26 +111,29 @@
|
|||
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-cpu-clk";
|
||||
compatible = "allwinner,sun4i-a10-cpu-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
|
||||
clock-output-names = "cpu";
|
||||
};
|
||||
|
||||
axi: axi@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-axi-clk";
|
||||
compatible = "allwinner,sun4i-a10-axi-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&cpu>;
|
||||
clock-output-names = "axi";
|
||||
};
|
||||
|
||||
ahb: ahb@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-ahb-clk";
|
||||
compatible = "allwinner,sun4i-a10-ahb-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&axi>;
|
||||
clock-output-names = "ahb";
|
||||
};
|
||||
|
||||
ahb_gates: ahb_gates@01c20060 {
|
||||
ahb_gates: clk@01c20060 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun7i-a20-ahb-gates-clk";
|
||||
reg = <0x01c20060 0x8>;
|
||||
|
|
@ -133,12 +155,13 @@
|
|||
|
||||
apb0: apb0@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb0-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb0-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&ahb>;
|
||||
clock-output-names = "apb0";
|
||||
};
|
||||
|
||||
apb0_gates: apb0_gates@01c20068 {
|
||||
apb0_gates: clk@01c20068 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun7i-a20-apb0-gates-clk";
|
||||
reg = <0x01c20068 0x4>;
|
||||
|
|
@ -151,19 +174,21 @@
|
|||
|
||||
apb1_mux: apb1_mux@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb1-mux-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1_mux";
|
||||
};
|
||||
|
||||
apb1: apb1@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb1-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb1-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&apb1_mux>;
|
||||
clock-output-names = "apb1";
|
||||
};
|
||||
|
||||
apb1_gates: apb1_gates@01c2006c {
|
||||
apb1_gates: clk@01c2006c {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun7i-a20-apb1-gates-clk";
|
||||
reg = <0x01c2006c 0x4>;
|
||||
|
|
@ -178,7 +203,7 @@
|
|||
|
||||
nand_clk: clk@01c20080 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20080 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "nand";
|
||||
|
|
@ -186,7 +211,7 @@
|
|||
|
||||
ms_clk: clk@01c20084 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20084 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ms";
|
||||
|
|
@ -194,7 +219,7 @@
|
|||
|
||||
mmc0_clk: clk@01c20088 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20088 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc0";
|
||||
|
|
@ -202,7 +227,7 @@
|
|||
|
||||
mmc1_clk: clk@01c2008c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c2008c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc1";
|
||||
|
|
@ -210,7 +235,7 @@
|
|||
|
||||
mmc2_clk: clk@01c20090 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20090 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc2";
|
||||
|
|
@ -218,7 +243,7 @@
|
|||
|
||||
mmc3_clk: clk@01c20094 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20094 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc3";
|
||||
|
|
@ -226,7 +251,7 @@
|
|||
|
||||
ts_clk: clk@01c20098 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20098 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ts";
|
||||
|
|
@ -234,7 +259,7 @@
|
|||
|
||||
ss_clk: clk@01c2009c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c2009c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ss";
|
||||
|
|
@ -242,7 +267,7 @@
|
|||
|
||||
spi0_clk: clk@01c200a0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi0";
|
||||
|
|
@ -250,7 +275,7 @@
|
|||
|
||||
spi1_clk: clk@01c200a4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi1";
|
||||
|
|
@ -258,7 +283,7 @@
|
|||
|
||||
spi2_clk: clk@01c200a8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a8 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi2";
|
||||
|
|
@ -266,7 +291,7 @@
|
|||
|
||||
pata_clk: clk@01c200ac {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200ac 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "pata";
|
||||
|
|
@ -274,7 +299,7 @@
|
|||
|
||||
ir0_clk: clk@01c200b0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200b0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ir0";
|
||||
|
|
@ -282,15 +307,24 @@
|
|||
|
||||
ir1_clk: clk@01c200b4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200b4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ir1";
|
||||
};
|
||||
|
||||
usb_clk: clk@01c200cc {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-usb-clk";
|
||||
reg = <0x01c200cc 0x4>;
|
||||
clocks = <&pll6 1>;
|
||||
clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
|
||||
};
|
||||
|
||||
spi3_clk: clk@01c200d4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200d4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi3";
|
||||
|
|
@ -298,12 +332,40 @@
|
|||
|
||||
mbus_clk: clk@01c2015c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c2015c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
|
||||
clock-output-names = "mbus";
|
||||
};
|
||||
|
||||
/*
|
||||
* The following two are dummy clocks, placeholders used in the gmac_tx
|
||||
* clock. The gmac driver will choose one parent depending on the PHY
|
||||
* interface mode, using clk_set_rate auto-reparenting.
|
||||
* The actual TX clock rate is not controlled by the gmac_tx clock.
|
||||
*/
|
||||
mii_phy_tx_clk: clk@2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "mii_phy_tx";
|
||||
};
|
||||
|
||||
gmac_int_tx_clk: clk@3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "gmac_int_tx";
|
||||
};
|
||||
|
||||
gmac_tx_clk: clk@01c20164 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun7i-a20-gmac-clk";
|
||||
reg = <0x01c20164 0x4>;
|
||||
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
|
||||
clock-output-names = "gmac_tx";
|
||||
};
|
||||
|
||||
/*
|
||||
* Dummy clock used by output clocks
|
||||
*/
|
||||
|
|
@ -339,6 +401,28 @@
|
|||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
spi0: spi@01c05000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c05000 0x1000>;
|
||||
interrupts = <0 10 4>;
|
||||
clocks = <&ahb_gates 20>, <&spi0_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1: spi@01c06000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c06000 0x1000>;
|
||||
interrupts = <0 11 4>;
|
||||
clocks = <&ahb_gates 21>, <&spi1_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emac: ethernet@01c0b000 {
|
||||
compatible = "allwinner,sun4i-a10-emac";
|
||||
reg = <0x01c0b000 0x1000>;
|
||||
|
|
@ -355,6 +439,28 @@
|
|||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi2: spi@01c17000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c17000 0x1000>;
|
||||
interrupts = <0 12 4>;
|
||||
clocks = <&ahb_gates 22>, <&spi2_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi3: spi@01c1f000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c1f000 0x1000>;
|
||||
interrupts = <0 50 4>;
|
||||
clocks = <&ahb_gates 23>, <&spi3_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
pio: pinctrl@01c20800 {
|
||||
compatible = "allwinner,sun7i-a20-pinctrl";
|
||||
reg = <0x01c20800 0x400>;
|
||||
|
|
@ -373,6 +479,13 @@
|
|||
allwinner,pull = <0>;
|
||||
};
|
||||
|
||||
uart2_pins_a: uart2@0 {
|
||||
allwinner,pins = "PI16", "PI17", "PI18", "PI19";
|
||||
allwinner,function = "uart2";
|
||||
allwinner,drive = <0>;
|
||||
allwinner,pull = <0>;
|
||||
};
|
||||
|
||||
uart6_pins_a: uart6@0 {
|
||||
allwinner,pins = "PI12", "PI13";
|
||||
allwinner,function = "uart6";
|
||||
|
|
@ -432,6 +545,46 @@
|
|||
allwinner,drive = <0>;
|
||||
allwinner,pull = <0>;
|
||||
};
|
||||
|
||||
gmac_pins_mii_a: gmac_mii@0 {
|
||||
allwinner,pins = "PA0", "PA1", "PA2",
|
||||
"PA3", "PA4", "PA5", "PA6",
|
||||
"PA7", "PA8", "PA9", "PA10",
|
||||
"PA11", "PA12", "PA13", "PA14",
|
||||
"PA15", "PA16";
|
||||
allwinner,function = "gmac";
|
||||
allwinner,drive = <0>;
|
||||
allwinner,pull = <0>;
|
||||
};
|
||||
|
||||
gmac_pins_rgmii_a: gmac_rgmii@0 {
|
||||
allwinner,pins = "PA0", "PA1", "PA2",
|
||||
"PA3", "PA4", "PA5", "PA6",
|
||||
"PA7", "PA8", "PA10",
|
||||
"PA11", "PA12", "PA13",
|
||||
"PA15", "PA16";
|
||||
allwinner,function = "gmac";
|
||||
/*
|
||||
* data lines in RGMII mode use DDR mode
|
||||
* and need a higher signal drive strength
|
||||
*/
|
||||
allwinner,drive = <3>;
|
||||
allwinner,pull = <0>;
|
||||
};
|
||||
|
||||
spi1_pins_a: spi1@0 {
|
||||
allwinner,pins = "PI16", "PI17", "PI18", "PI19";
|
||||
allwinner,function = "spi1";
|
||||
allwinner,drive = <0>;
|
||||
allwinner,pull = <0>;
|
||||
};
|
||||
|
||||
spi2_pins_a: spi2@0 {
|
||||
allwinner,pins = "PC19", "PC20", "PC21", "PC22";
|
||||
allwinner,function = "spi2";
|
||||
allwinner,drive = <0>;
|
||||
allwinner,pull = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
timer@01c20c00 {
|
||||
|
|
@ -593,6 +746,21 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac: ethernet@01c50000 {
|
||||
compatible = "allwinner,sun7i-a20-gmac";
|
||||
reg = <0x01c50000 0x10000>;
|
||||
interrupts = <0 85 4>;
|
||||
interrupt-names = "macirq";
|
||||
clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
|
||||
clock-names = "stmmaceth", "allwinner_gmac_tx";
|
||||
snps,pbl = <2>;
|
||||
snps,fixed-burst;
|
||||
snps,force_sf_dma_mode;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
hstimer@01c60000 {
|
||||
compatible = "allwinner,sun7i-a20-hstimer";
|
||||
reg = <0x01c60000 0x1000>;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue