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sh: sh7785 pll configuration from mode pin

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This patch modifies the sh7785 clock code to use the MODE4
value to switch between 72x and 36x PLL multiplication.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm 2009-05-28 12:06:17 +00:00 • committed by Paul Mundt
parent 63d12e2323
commit 1823f6d5e6
1 changed files with 6 additions and 6 deletions
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12
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
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@ -16,6 +16,7 @@
#include <linux/cpufreq.h> #include <linux/cpufreq.h>
#include <asm/clock.h> #include <asm/clock.h>
#include <asm/freq.h> #include <asm/freq.h>
#include <cpu/sh7785.h>
static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
24, 32, 36, 48 }; 24, 32, 36, 48 };
@ -80,12 +81,11 @@ static struct clk_ops frqmr_clk_ops = {
static unsigned long pll_recalc(struct clk *clk) static unsigned long pll_recalc(struct clk *clk)
{ {
/* int multiplier;
* XXX: PLL1 multiplier is locked for the default clock mode,
* when mode pin detection and configuration support is added, multiplier = test_mode_pin(MODE_PIN_MODE4) ? 36 : 72;
* select the multiplier dynamically.
*/ return clk->parent->rate * multiplier;
return clk->parent->rate * 36;
} }
static struct clk_ops pll_clk_ops = { static struct clk_ops pll_clk_ops = {