power: qpnp-fg-gen3: improve cycle counter algorithm
Currently, when the charging status transitions to a state other than charging, cycle counter algorithm stores the cycle count for all the buckets for which the counting had started. This is fine with respect to the algorithm. However with qnovo enabled charging, this can cause issues when charging status can go to not charging intermittently causing the cycle count to be stored multiple times for a bucket. Modify the logic to check for the charge termination or the presence of input to go through all the buckets for storing the count. Also, increment and store the counter only if battery SOC had increased more than 2 LSBs for that SOC bucket. While at it, run cycle_counter algorithm as a function instead of a work. Also, keep the usage of cycle counter feature enable flag inside the cycle counter APIs. Change-Id: I62a92964ccbc6b965af09696deddc6fa8366a841 Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org> Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
This commit is contained in:
Subbaraman Narayanamurthy
Nicholas Troast
parent
96168e19d4
commit
183bc63f12
2 changed files with 103 additions and 121 deletions
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@ -49,7 +49,6 @@
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#define SRAM_READ "fg_sram_read"
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#define SRAM_WRITE "fg_sram_write"
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#define PROFILE_LOAD "fg_profile_load"
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#define DELTA_SOC "fg_delta_soc"
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#define TTF_PRIMING "fg_ttf_priming"
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/* Delta BSOC irq votable reasons */
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@ -438,7 +437,6 @@ struct fg_chip {
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struct completion soc_ready;
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struct delayed_work profile_load_work;
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struct work_struct status_change_work;
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struct work_struct cycle_count_work;
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struct delayed_work ttf_work;
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struct delayed_work sram_dump_work;
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};
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@ -2231,94 +2231,14 @@ static void fg_ttf_update(struct fg_chip *chip)
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schedule_delayed_work(&chip->ttf_work, msecs_to_jiffies(delay_ms));
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}
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static void status_change_work(struct work_struct *work)
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{
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struct fg_chip *chip = container_of(work,
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struct fg_chip, status_change_work);
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union power_supply_propval prop = {0, };
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int rc, batt_temp;
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if (!batt_psy_initialized(chip)) {
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fg_dbg(chip, FG_STATUS, "Charger not available?!\n");
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goto out;
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}
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rc = power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_STATUS,
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&prop);
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if (rc < 0) {
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pr_err("Error in getting charging status, rc=%d\n", rc);
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goto out;
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}
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chip->prev_charge_status = chip->charge_status;
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chip->charge_status = prop.intval;
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rc = power_supply_get_property(chip->batt_psy,
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POWER_SUPPLY_PROP_CHARGE_TYPE, &prop);
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if (rc < 0) {
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pr_err("Error in getting charge type, rc=%d\n", rc);
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goto out;
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}
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chip->charge_type = prop.intval;
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rc = power_supply_get_property(chip->batt_psy,
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POWER_SUPPLY_PROP_CHARGE_DONE, &prop);
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if (rc < 0) {
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pr_err("Error in getting charge_done, rc=%d\n", rc);
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goto out;
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}
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chip->charge_done = prop.intval;
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if (chip->cyc_ctr.en)
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schedule_work(&chip->cycle_count_work);
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fg_cap_learning_update(chip);
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rc = fg_charge_full_update(chip);
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if (rc < 0)
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pr_err("Error in charge_full_update, rc=%d\n", rc);
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rc = fg_adjust_recharge_soc(chip);
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if (rc < 0)
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pr_err("Error in adjusting recharge_soc, rc=%d\n", rc);
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rc = fg_adjust_ki_coeff_dischg(chip);
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if (rc < 0)
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pr_err("Error in adjusting ki_coeff_dischg, rc=%d\n", rc);
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rc = fg_esr_fcc_config(chip);
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if (rc < 0)
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pr_err("Error in adjusting FCC for ESR, rc=%d\n", rc);
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rc = fg_esr_timer_config(chip, false);
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if (rc < 0)
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pr_err("Error in configuring ESR timer, rc=%d\n", rc);
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rc = fg_get_battery_temp(chip, &batt_temp);
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if (!rc) {
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rc = fg_slope_limit_config(chip, batt_temp);
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if (rc < 0)
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pr_err("Error in configuring slope limiter rc:%d\n",
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rc);
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rc = fg_adjust_ki_coeff_full_soc(chip, batt_temp);
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if (rc < 0)
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pr_err("Error in configuring ki_coeff_full_soc rc:%d\n",
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rc);
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}
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fg_ttf_update(chip);
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out:
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fg_dbg(chip, FG_POWER_SUPPLY, "charge_status:%d charge_type:%d charge_done:%d\n",
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chip->charge_status, chip->charge_type, chip->charge_done);
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pm_relax(chip->dev);
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}
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static void restore_cycle_counter(struct fg_chip *chip)
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{
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int rc = 0, i;
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u8 data[2];
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if (!chip->cyc_ctr.en)
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return;
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mutex_lock(&chip->cyc_ctr.lock);
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for (i = 0; i < BUCKET_COUNT; i++) {
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rc = fg_sram_read(chip, CYCLE_COUNT_WORD + (i / 2),
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@ -2372,20 +2292,25 @@ static int fg_inc_store_cycle_ctr(struct fg_chip *chip, int bucket)
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rc = fg_sram_write(chip, CYCLE_COUNT_WORD + (bucket / 2),
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CYCLE_COUNT_OFFSET + (bucket % 2) * 2, data, 2,
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FG_IMA_DEFAULT);
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if (rc < 0)
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if (rc < 0) {
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pr_err("failed to write BATT_CYCLE[%d] rc=%d\n",
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bucket, rc);
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else
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chip->cyc_ctr.count[bucket] = cyc_count;
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return rc;
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}
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chip->cyc_ctr.count[bucket] = cyc_count;
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fg_dbg(chip, FG_STATUS, "Stored count %d in bucket %d\n", cyc_count,
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bucket);
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return rc;
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}
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static void cycle_count_work(struct work_struct *work)
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static void fg_cycle_counter_update(struct fg_chip *chip)
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{
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int rc = 0, bucket, i, batt_soc;
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struct fg_chip *chip = container_of(work,
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struct fg_chip,
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cycle_count_work);
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if (!chip->cyc_ctr.en)
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return;
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mutex_lock(&chip->cyc_ctr.lock);
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rc = fg_get_sram_prop(chip, FG_SRAM_BATT_SOC, &batt_soc);
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@ -2397,45 +2322,30 @@ static void cycle_count_work(struct work_struct *work)
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/* We need only the most significant byte here */
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batt_soc = (u32)batt_soc >> 24;
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if (chip->charge_status == POWER_SUPPLY_STATUS_CHARGING) {
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/* Find out which bucket the SOC falls in */
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bucket = batt_soc / BUCKET_SOC_PCT;
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pr_debug("batt_soc: %d bucket: %d\n", batt_soc, bucket);
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/* Find out which bucket the SOC falls in */
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bucket = batt_soc / BUCKET_SOC_PCT;
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/*
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* If we've started counting for the previous bucket,
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* then store the counter for that bucket if the
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* counter for current bucket is getting started.
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*/
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if (bucket > 0 && chip->cyc_ctr.started[bucket - 1] &&
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!chip->cyc_ctr.started[bucket]) {
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rc = fg_inc_store_cycle_ctr(chip, bucket - 1);
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if (rc < 0) {
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pr_err("Error in storing cycle_ctr rc: %d\n",
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rc);
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goto out;
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} else {
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chip->cyc_ctr.started[bucket - 1] = false;
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chip->cyc_ctr.last_soc[bucket - 1] = 0;
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}
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}
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if (chip->charge_status == POWER_SUPPLY_STATUS_CHARGING) {
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if (!chip->cyc_ctr.started[bucket]) {
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chip->cyc_ctr.started[bucket] = true;
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chip->cyc_ctr.last_soc[bucket] = batt_soc;
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}
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} else {
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} else if (chip->charge_done || !is_input_present(chip)) {
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for (i = 0; i < BUCKET_COUNT; i++) {
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if (chip->cyc_ctr.started[i] &&
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batt_soc > chip->cyc_ctr.last_soc[i]) {
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batt_soc > chip->cyc_ctr.last_soc[i] + 2) {
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rc = fg_inc_store_cycle_ctr(chip, i);
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if (rc < 0)
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pr_err("Error in storing cycle_ctr rc: %d\n",
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rc);
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chip->cyc_ctr.last_soc[i] = 0;
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chip->cyc_ctr.started[i] = false;
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}
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chip->cyc_ctr.started[i] = false;
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}
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}
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fg_dbg(chip, FG_STATUS, "batt_soc: %d bucket: %d chg_status: %d\n",
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batt_soc, bucket, chip->charge_status);
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out:
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mutex_unlock(&chip->cyc_ctr.lock);
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}
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@ -2456,6 +2366,83 @@ static int fg_get_cycle_count(struct fg_chip *chip)
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return count;
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}
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static void status_change_work(struct work_struct *work)
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{
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struct fg_chip *chip = container_of(work,
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struct fg_chip, status_change_work);
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union power_supply_propval prop = {0, };
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int rc, batt_temp;
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if (!batt_psy_initialized(chip)) {
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fg_dbg(chip, FG_STATUS, "Charger not available?!\n");
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goto out;
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}
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rc = power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_STATUS,
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&prop);
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if (rc < 0) {
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pr_err("Error in getting charging status, rc=%d\n", rc);
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goto out;
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}
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chip->prev_charge_status = chip->charge_status;
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chip->charge_status = prop.intval;
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rc = power_supply_get_property(chip->batt_psy,
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POWER_SUPPLY_PROP_CHARGE_TYPE, &prop);
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if (rc < 0) {
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pr_err("Error in getting charge type, rc=%d\n", rc);
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goto out;
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}
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chip->charge_type = prop.intval;
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rc = power_supply_get_property(chip->batt_psy,
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POWER_SUPPLY_PROP_CHARGE_DONE, &prop);
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if (rc < 0) {
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pr_err("Error in getting charge_done, rc=%d\n", rc);
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goto out;
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}
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chip->charge_done = prop.intval;
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fg_cycle_counter_update(chip);
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fg_cap_learning_update(chip);
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rc = fg_charge_full_update(chip);
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if (rc < 0)
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pr_err("Error in charge_full_update, rc=%d\n", rc);
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rc = fg_adjust_recharge_soc(chip);
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if (rc < 0)
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pr_err("Error in adjusting recharge_soc, rc=%d\n", rc);
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rc = fg_adjust_ki_coeff_dischg(chip);
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if (rc < 0)
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pr_err("Error in adjusting ki_coeff_dischg, rc=%d\n", rc);
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rc = fg_esr_fcc_config(chip);
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if (rc < 0)
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pr_err("Error in adjusting FCC for ESR, rc=%d\n", rc);
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rc = fg_get_battery_temp(chip, &batt_temp);
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if (!rc) {
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rc = fg_slope_limit_config(chip, batt_temp);
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if (rc < 0)
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pr_err("Error in configuring slope limiter rc:%d\n",
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rc);
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rc = fg_adjust_ki_coeff_full_soc(chip, batt_temp);
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if (rc < 0)
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pr_err("Error in configuring ki_coeff_full_soc rc:%d\n",
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rc);
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}
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fg_ttf_update(chip);
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out:
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fg_dbg(chip, FG_POWER_SUPPLY, "charge_status:%d charge_type:%d charge_done:%d\n",
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chip->charge_status, chip->charge_type, chip->charge_done);
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pm_relax(chip->dev);
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}
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static int fg_bp_params_config(struct fg_chip *chip)
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{
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int rc = 0;
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@ -3755,8 +3742,7 @@ static int fg_hw_init(struct fg_chip *chip)
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return rc;
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}
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if (chip->cyc_ctr.en)
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restore_cycle_counter(chip);
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restore_cycle_counter(chip);
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if (chip->dt.jeita_hyst_temp >= 0) {
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val = chip->dt.jeita_hyst_temp << JEITA_TEMP_HYST_SHIFT;
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@ -4030,8 +4016,7 @@ static irqreturn_t fg_delta_msoc_irq_handler(int irq, void *data)
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int rc;
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fg_dbg(chip, FG_IRQ, "irq %d triggered\n", irq);
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if (chip->cyc_ctr.en)
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schedule_work(&chip->cycle_count_work);
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fg_cycle_counter_update(chip);
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if (chip->cl.active)
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fg_cap_learning_update(chip);
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@ -4801,7 +4786,6 @@ static int fg_gen3_probe(struct platform_device *pdev)
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init_completion(&chip->soc_ready);
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INIT_DELAYED_WORK(&chip->profile_load_work, profile_load_work);
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INIT_WORK(&chip->status_change_work, status_change_work);
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INIT_WORK(&chip->cycle_count_work, cycle_count_work);
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INIT_DELAYED_WORK(&chip->ttf_work, ttf_work);
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INIT_DELAYED_WORK(&chip->sram_dump_work, sram_dump_work);
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