clk: msm: clock: Gate the limits clock during certain sleep states

Program the DROOP_CODE register for both clusters so that
the limits management clock is gated off during certain
sleep states.

CRs-Fixed: 973567
Change-Id: If4860d329393ece54a4d0f017c2700d4bde9d2b6
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
This commit is contained in:
Deepak Katragadda 2016-02-08 12:10:36 -08:00 committed by David Keitel
parent dc29065dc2
commit 18e5e80ee9

View file

@ -1760,11 +1760,12 @@ int __init cpu_clock_8996_early_init(void)
if (cpu_clocks_pro) {
/*
* Configure ACS logic to switch to always-on clock
* source during D2-D5 entry
* source during D2-D5 entry. In addition, gate the
* limits management clock during certain sleep states.
*/
writel_relaxed(0x1, vbases[APC0_BASE] +
writel_relaxed(0x3, vbases[APC0_BASE] +
MDD_DROOP_CODE);
writel_relaxed(0x1, vbases[APC1_BASE] +
writel_relaxed(0x3, vbases[APC1_BASE] +
MDD_DROOP_CODE);
/*
* Ensure that the writes go through before enabling