clk: msm: clock: Gate the limits clock during certain sleep states
Program the DROOP_CODE register for both clusters so that the limits management clock is gated off during certain sleep states. CRs-Fixed: 973567 Change-Id: If4860d329393ece54a4d0f017c2700d4bde9d2b6 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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1 changed files with 4 additions and 3 deletions
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@ -1760,11 +1760,12 @@ int __init cpu_clock_8996_early_init(void)
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if (cpu_clocks_pro) {
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/*
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* Configure ACS logic to switch to always-on clock
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* source during D2-D5 entry
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* source during D2-D5 entry. In addition, gate the
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* limits management clock during certain sleep states.
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*/
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writel_relaxed(0x1, vbases[APC0_BASE] +
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writel_relaxed(0x3, vbases[APC0_BASE] +
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MDD_DROOP_CODE);
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writel_relaxed(0x1, vbases[APC1_BASE] +
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writel_relaxed(0x3, vbases[APC1_BASE] +
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MDD_DROOP_CODE);
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/*
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* Ensure that the writes go through before enabling
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