msm: kgsl: restructure GPU power initialization
Move target specific initialization and setup into target specific init functions. The change is required to port the GPU driver to support future generation GPUs. CRs-Fixed: 1053516 Change-Id: I808e247669fab61a6a64131858fe2f9e19754242 Signed-off-by: George Shen <sqiao@codeaurora.org>
This commit is contained in:
George Shen
parent
1fac7f53bd
commit
19baa2bf45
4 changed files with 160 additions and 159 deletions
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@ -1242,86 +1242,6 @@ static bool regulators_left_on(struct kgsl_device *device)
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return false;
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}
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static void _setup_throttling_counters(struct adreno_device *adreno_dev)
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{
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int i, ret;
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if (!adreno_is_a540(adreno_dev))
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return;
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if (!ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))
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return;
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for (i = 0; i < ADRENO_GPMU_THROTTLE_COUNTERS; i++) {
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/* reset throttled cycles ivalue */
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adreno_dev->busy_data.throttle_cycles[i] = 0;
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if (adreno_dev->gpmu_throttle_counters[i] != 0)
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continue;
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ret = adreno_perfcounter_get(adreno_dev,
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KGSL_PERFCOUNTER_GROUP_GPMU_PWR,
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ADRENO_GPMU_THROTTLE_COUNTERS_BASE_REG + i,
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&adreno_dev->gpmu_throttle_counters[i],
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NULL,
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PERFCOUNTER_FLAG_KERNEL);
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WARN_ONCE(ret, "Unable to get clock throttling counter %x\n",
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ADRENO_GPMU_THROTTLE_COUNTERS_BASE_REG + i);
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}
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}
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/* FW driven idle 10% throttle */
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#define IDLE_10PCT 0
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/* number of cycles when clock is throttled by 50% (CRC) */
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#define CRC_50PCT 1
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/* number of cycles when clock is throttled by more than 50% (CRC) */
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#define CRC_MORE50PCT 2
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/* number of cycles when clock is throttle by less than 50% (CRC) */
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#define CRC_LESS50PCT 3
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static uint64_t _read_throttling_counters(struct adreno_device *adreno_dev)
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{
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int i, adj;
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uint32_t th[ADRENO_GPMU_THROTTLE_COUNTERS];
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struct adreno_busy_data *busy = &adreno_dev->busy_data;
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if (!adreno_is_a540(adreno_dev))
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return 0;
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if (!ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))
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return 0;
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if (!test_bit(ADRENO_THROTTLING_CTRL, &adreno_dev->pwrctrl_flag))
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return 0;
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for (i = 0; i < ADRENO_GPMU_THROTTLE_COUNTERS; i++) {
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if (!adreno_dev->gpmu_throttle_counters[i])
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return 0;
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th[i] = counter_delta(KGSL_DEVICE(adreno_dev),
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adreno_dev->gpmu_throttle_counters[i],
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&busy->throttle_cycles[i]);
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}
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adj = th[CRC_MORE50PCT] - th[IDLE_10PCT];
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adj = th[CRC_50PCT] + th[CRC_LESS50PCT] / 3 + (adj < 0 ? 0 : adj) * 3;
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trace_kgsl_clock_throttling(
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th[IDLE_10PCT], th[CRC_50PCT],
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th[CRC_MORE50PCT], th[CRC_LESS50PCT],
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adj);
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return adj;
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}
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static void _update_threshold_count(struct adreno_device *adreno_dev,
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uint64_t adj)
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{
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if (adreno_is_a530(adreno_dev))
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kgsl_regread(KGSL_DEVICE(adreno_dev),
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adreno_dev->lm_threshold_count,
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&adreno_dev->lm_threshold_cross);
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else if (adreno_is_a540(adreno_dev))
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adreno_dev->lm_threshold_cross = adj;
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}
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static void _set_secvid(struct kgsl_device *device)
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{
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struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
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@ -1418,8 +1338,8 @@ static int _adreno_start(struct adreno_device *adreno_dev)
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}
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}
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if (device->pwrctrl.bus_control) {
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if (device->pwrctrl.bus_control) {
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/* VBIF waiting for RAM */
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if (adreno_dev->starved_ram_lo == 0) {
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ret = adreno_perfcounter_get(adreno_dev,
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@ -1455,20 +1375,6 @@ static int _adreno_start(struct adreno_device *adreno_dev)
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adreno_dev->busy_data.vbif_ram_cycles = 0;
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adreno_dev->busy_data.vbif_starved_ram = 0;
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if (adreno_is_a530(adreno_dev) && ADRENO_FEATURE(adreno_dev, ADRENO_LM)
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&& adreno_dev->lm_threshold_count == 0) {
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ret = adreno_perfcounter_get(adreno_dev,
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KGSL_PERFCOUNTER_GROUP_GPMU_PWR, 27,
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&adreno_dev->lm_threshold_count, NULL,
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PERFCOUNTER_FLAG_KERNEL);
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/* Ignore noncritical ret - used for debugfs */
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if (ret)
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adreno_dev->lm_threshold_count = 0;
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}
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_setup_throttling_counters(adreno_dev);
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/* Restore performance counter registers with saved values */
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adreno_perfcounter_restore(adreno_dev);
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@ -2580,27 +2486,6 @@ static inline s64 adreno_ticks_to_us(u32 ticks, u32 freq)
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return ticks / freq;
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}
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static unsigned int counter_delta(struct kgsl_device *device,
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unsigned int reg, unsigned int *counter)
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{
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unsigned int val;
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unsigned int ret = 0;
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/* Read the value */
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kgsl_regread(device, reg, &val);
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/* Return 0 for the first read */
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if (*counter != 0) {
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if (val < *counter)
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ret = (0xFFFFFFFF - *counter) + val;
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else
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ret = val - *counter;
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}
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*counter = val;
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return ret;
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}
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/**
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* adreno_power_stats() - Reads the counters needed for freq decisions
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* @device: Pointer to device whose counters are read
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@ -2612,6 +2497,7 @@ static void adreno_power_stats(struct kgsl_device *device,
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struct kgsl_power_stats *stats)
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{
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struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
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struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
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struct kgsl_pwrctrl *pwr = &device->pwrctrl;
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struct adreno_busy_data *busy = &adreno_dev->busy_data;
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uint64_t adj = 0;
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@ -2625,8 +2511,11 @@ static void adreno_power_stats(struct kgsl_device *device,
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gpu_busy = counter_delta(device, adreno_dev->perfctr_pwr_lo,
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&busy->gpu_busy);
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adj = _read_throttling_counters(adreno_dev);
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gpu_busy += adj;
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if (gpudev->read_throttling_counters) {
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adj = gpudev->read_throttling_counters(adreno_dev);
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gpu_busy += adj;
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}
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stats->busy_time = adreno_ticks_to_us(gpu_busy,
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kgsl_pwrctrl_active_freq(pwr));
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}
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@ -2647,8 +2536,9 @@ static void adreno_power_stats(struct kgsl_device *device,
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stats->ram_time = ram_cycles;
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stats->ram_wait = starved_ram;
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}
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if (adreno_dev->lm_threshold_count)
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_update_threshold_count(adreno_dev, adj);
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if (adreno_dev->lm_threshold_count &&
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gpudev->count_throttles)
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gpudev->count_throttles(adreno_dev, adj);
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}
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static unsigned int adreno_gpuid(struct kgsl_device *device,
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@ -756,6 +756,10 @@ struct adreno_gpudev {
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void (*pwrlevel_change_settings)(struct adreno_device *,
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unsigned int prelevel, unsigned int postlevel,
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bool post);
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uint64_t (*read_throttling_counters)(struct adreno_device *);
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void (*count_throttles)(struct adreno_device *, uint64_t adj);
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int (*enable_pwr_counters)(struct adreno_device *,
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unsigned int counter);
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unsigned int (*preemption_pre_ibsubmit)(struct adreno_device *,
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struct adreno_ringbuffer *rb,
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unsigned int *, struct kgsl_context *);
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@ -1467,4 +1471,24 @@ static inline void adreno_ringbuffer_set_pagetable(struct adreno_ringbuffer *rb,
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spin_unlock_irqrestore(&rb->preempt_lock, flags);
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}
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static inline unsigned int counter_delta(struct kgsl_device *device,
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unsigned int reg, unsigned int *counter)
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{
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unsigned int val;
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unsigned int ret = 0;
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/* Read the value */
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kgsl_regread(device, reg, &val);
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/* Return 0 for the first read */
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if (*counter != 0) {
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if (val < *counter)
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ret = (0xFFFFFFFF - *counter) + val;
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else
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ret = val - *counter;
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}
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*counter = val;
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return ret;
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}
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#endif /*__ADRENO_H */
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@ -27,6 +27,7 @@
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#include "kgsl_sharedmem.h"
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#include "kgsl_log.h"
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#include "kgsl.h"
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#include "kgsl_trace.h"
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#include "adreno_a5xx_packets.h"
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static int zap_ucode_loaded;
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@ -1646,6 +1647,76 @@ static void a5xx_clk_set_options(struct adreno_device *adreno_dev,
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}
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}
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static void a5xx_count_throttles(struct adreno_device *adreno_dev,
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uint64_t adj)
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{
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if (adreno_is_a530(adreno_dev))
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kgsl_regread(KGSL_DEVICE(adreno_dev),
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adreno_dev->lm_threshold_count,
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&adreno_dev->lm_threshold_cross);
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else if (adreno_is_a540(adreno_dev))
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adreno_dev->lm_threshold_cross = adj;
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}
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static int a5xx_enable_pwr_counters(struct adreno_device *adreno_dev,
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unsigned int counter)
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{
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/*
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* On 5XX we have to emulate the PWR counters which are physically
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* missing. Program countable 6 on RBBM_PERFCTR_RBBM_0 as a substitute
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* for PWR:1. Don't emulate PWR:0 as nobody uses it and we don't want
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* to take away too many of the generic RBBM counters.
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*/
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if (counter == 0)
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return -EINVAL;
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kgsl_regwrite(KGSL_DEVICE(adreno_dev), A5XX_RBBM_PERFCTR_RBBM_SEL_0, 6);
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return 0;
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}
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/* FW driven idle 10% throttle */
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#define IDLE_10PCT 0
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/* number of cycles when clock is throttled by 50% (CRC) */
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#define CRC_50PCT 1
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/* number of cycles when clock is throttled by more than 50% (CRC) */
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#define CRC_MORE50PCT 2
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/* number of cycles when clock is throttle by less than 50% (CRC) */
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#define CRC_LESS50PCT 3
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static uint64_t a5xx_read_throttling_counters(struct adreno_device *adreno_dev)
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{
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int i, adj;
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uint32_t th[ADRENO_GPMU_THROTTLE_COUNTERS];
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struct adreno_busy_data *busy = &adreno_dev->busy_data;
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if (!adreno_is_a540(adreno_dev))
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return 0;
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if (!ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))
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return 0;
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if (!test_bit(ADRENO_THROTTLING_CTRL, &adreno_dev->pwrctrl_flag))
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return 0;
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for (i = 0; i < ADRENO_GPMU_THROTTLE_COUNTERS; i++) {
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if (!adreno_dev->gpmu_throttle_counters[i])
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return 0;
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th[i] = counter_delta(KGSL_DEVICE(adreno_dev),
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adreno_dev->gpmu_throttle_counters[i],
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&busy->throttle_cycles[i]);
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}
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adj = th[CRC_MORE50PCT] - th[IDLE_10PCT];
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adj = th[CRC_50PCT] + th[CRC_LESS50PCT] / 3 + (adj < 0 ? 0 : adj) * 3;
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trace_kgsl_clock_throttling(
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th[IDLE_10PCT], th[CRC_50PCT],
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th[CRC_MORE50PCT], th[CRC_LESS50PCT],
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adj);
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return adj;
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}
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static void a5xx_enable_64bit(struct adreno_device *adreno_dev)
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{
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@ -1712,12 +1783,44 @@ static void a5xx_gpmu_reset(struct work_struct *work)
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/* Soft reset of the GPMU block */
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kgsl_regwrite(device, A5XX_RBBM_BLOCK_SW_RESET_CMD, BIT(16));
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/* GPU comes up in secured mode, make it unsecured by default */
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if (!ADRENO_FEATURE(adreno_dev, ADRENO_CONTENT_PROTECTION))
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kgsl_regwrite(device, A5XX_RBBM_SECVID_TRUST_CNTL, 0x0);
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a5xx_gpmu_init(adreno_dev);
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out:
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mutex_unlock(&device->mutex);
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}
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static void _setup_throttling_counters(struct adreno_device *adreno_dev)
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{
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int i, ret;
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if (!adreno_is_a540(adreno_dev))
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return;
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if (!ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))
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return;
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for (i = 0; i < ADRENO_GPMU_THROTTLE_COUNTERS; i++) {
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/* reset throttled cycles ivalue */
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adreno_dev->busy_data.throttle_cycles[i] = 0;
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if (adreno_dev->gpmu_throttle_counters[i] != 0)
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continue;
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ret = adreno_perfcounter_get(adreno_dev,
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KGSL_PERFCOUNTER_GROUP_GPMU_PWR,
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ADRENO_GPMU_THROTTLE_COUNTERS_BASE_REG + i,
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&adreno_dev->gpmu_throttle_counters[i],
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NULL,
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PERFCOUNTER_FLAG_KERNEL);
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WARN_ONCE(ret, "Unable to get clock throttling counter %x\n",
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ADRENO_GPMU_THROTTLE_COUNTERS_BASE_REG + i);
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}
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}
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/*
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* a5xx_start() - Device start
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* @adreno_dev: Pointer to adreno device
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@ -1729,6 +1832,21 @@ static void a5xx_start(struct adreno_device *adreno_dev)
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
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unsigned int bit;
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int ret;
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if (adreno_is_a530(adreno_dev) && ADRENO_FEATURE(adreno_dev, ADRENO_LM)
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&& adreno_dev->lm_threshold_count == 0) {
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ret = adreno_perfcounter_get(adreno_dev,
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KGSL_PERFCOUNTER_GROUP_GPMU_PWR, 27,
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&adreno_dev->lm_threshold_count, NULL,
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PERFCOUNTER_FLAG_KERNEL);
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/* Ignore noncritical ret - used for debugfs */
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if (ret)
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adreno_dev->lm_threshold_count = 0;
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}
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_setup_throttling_counters(adreno_dev);
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adreno_vbif_start(adreno_dev, a5xx_vbif_platforms,
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ARRAY_SIZE(a5xx_vbif_platforms));
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@ -2034,11 +2152,6 @@ static int a5xx_post_start(struct adreno_device *adreno_dev)
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static int a5xx_gpmu_init(struct adreno_device *adreno_dev)
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{
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int ret;
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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/* GPU comes up in secured mode, make it unsecured by default */
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if (!ADRENO_FEATURE(adreno_dev, ADRENO_CONTENT_PROTECTION))
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kgsl_regwrite(device, A5XX_RBBM_SECVID_TRUST_CNTL, 0x0);
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/* Set up LM before initializing the GPMU */
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a5xx_lm_init(adreno_dev);
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@ -2359,20 +2472,10 @@ static int a5xx_rb_start(struct adreno_device *adreno_dev,
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if (ret)
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return ret;
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/* Set up LM before initializing the GPMU */
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a5xx_lm_init(adreno_dev);
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/* Enable SPTP based power collapse before enabling GPMU */
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a5xx_enable_pc(adreno_dev);
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/* Program the GPMU */
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ret = a5xx_gpmu_start(adreno_dev);
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ret = a5xx_gpmu_init(adreno_dev);
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if (ret)
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return ret;
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/* Enable limits management */
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a5xx_lm_enable(adreno_dev);
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a5xx_post_start(adreno_dev);
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return 0;
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@ -3534,6 +3637,9 @@ struct adreno_gpudev adreno_a5xx_gpudev = {
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.regulator_enable = a5xx_regulator_enable,
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.regulator_disable = a5xx_regulator_disable,
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.pwrlevel_change_settings = a5xx_pwrlevel_change_settings,
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.read_throttling_counters = a5xx_read_throttling_counters,
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.count_throttles = a5xx_count_throttles,
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.enable_pwr_counters = a5xx_enable_pwr_counters,
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.preemption_pre_ibsubmit = a5xx_preemption_pre_ibsubmit,
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.preemption_yield_enable =
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a5xx_preemption_yield_enable,
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@ -598,28 +598,6 @@ int adreno_perfcounter_put(struct adreno_device *adreno_dev,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int _perfcounter_enable_pwr(struct adreno_device *adreno_dev,
|
||||
unsigned int counter)
|
||||
{
|
||||
/* PWR counters enabled by default on A3XX/A4XX so nothing to do */
|
||||
if (adreno_is_a3xx(adreno_dev) || adreno_is_a4xx(adreno_dev))
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* On 5XX we have to emulate the PWR counters which are physically
|
||||
* missing. Program countable 6 on RBBM_PERFCTR_RBBM_0 as a substitute
|
||||
* for PWR:1. Don't emulate PWR:0 as nobody uses it and we don't want
|
||||
* to take away too many of the generic RBBM counters.
|
||||
*/
|
||||
|
||||
if (counter == 0)
|
||||
return -EINVAL;
|
||||
|
||||
kgsl_regwrite(KGSL_DEVICE(adreno_dev), A5XX_RBBM_PERFCTR_RBBM_SEL_0, 6);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void _perfcounter_enable_vbif(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcounters *counters, unsigned int counter,
|
||||
unsigned int countable)
|
||||
|
|
@ -771,6 +749,7 @@ static int adreno_perfcounter_enable(struct adreno_device *adreno_dev,
|
|||
unsigned int group, unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
|
||||
|
||||
if (counters == NULL)
|
||||
return -EINVAL;
|
||||
|
|
@ -786,7 +765,9 @@ static int adreno_perfcounter_enable(struct adreno_device *adreno_dev,
|
|||
/* alwayson counter is global, so init value is 0 */
|
||||
break;
|
||||
case KGSL_PERFCOUNTER_GROUP_PWR:
|
||||
return _perfcounter_enable_pwr(adreno_dev, counter);
|
||||
if (gpudev->enable_pwr_counters)
|
||||
return gpudev->enable_pwr_counters(adreno_dev, counter);
|
||||
return 0;
|
||||
case KGSL_PERFCOUNTER_GROUP_VBIF:
|
||||
if (countable > VBIF2_PERF_CNT_SEL_MASK)
|
||||
return -EINVAL;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue