clk: msm: mdss: increase VCO frequency to above 8.9Ghz
For some resolutions on MSM8996 V2, PLL can become unlocked at high operating temperatures. To prevent this, use a VCO frequency of at least 8.9Ghz for bit clocks of at least 282Mhz. Change-Id: I409f286d23a924eab8bcd204638602e530597d77 Signed-off-by: Casey Piper <cpiper@codeaurora.org>
This commit is contained in:
Casey Piper
David Keitel
parent
ed2f52f863
commit
19ccabc6b7
1 changed files with 38 additions and 32 deletions
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@ -36,6 +36,7 @@
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#define HDMI_VERSION_8996_V2 2
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#define HDMI_2400MHZ_BIT_CLK_HZ 2400000000
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#define HDMI_2250MHZ_BIT_CLK_HZ 2250000000
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#define HDMI_2000MHZ_BIT_CLK_HZ 2000000000
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#define HDMI_1700MHZ_BIT_CLK_HZ 1700000000
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#define HDMI_1200MHZ_BIT_CLK_HZ 1200000000
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@ -48,6 +49,7 @@
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#define HDMI_450MHZ_BIT_CLK_HZ 450000000
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#define HDMI_334MHZ_BIT_CLK_HZ 334000000
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#define HDMI_300MHZ_BIT_CLK_HZ 300000000
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#define HDMI_282MHZ_BIT_CLK_HZ 282000000
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#define HDMI_250MHZ_BIT_CLK_HZ 250000000
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/* PLL REGISTERS */
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@ -386,34 +388,34 @@ static inline u64 hdmi_8996_v1_get_post_div_lt_2g(u64 bclk)
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return HDMI_64B_ERR_VAL;
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}
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static inline u64 hdmi_8996_v2_get_post_div_lt_2g(u64 bclk)
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static inline u64 hdmi_8996_v2_get_post_div_lt_2g(u64 bclk, u64 vco_range)
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{
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u64 hdmi_8ghz = (u64)HDMI_2000MHZ_BIT_CLK_HZ;
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u64 hdmi_8ghz = vco_range;
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u64 tmp_calc;
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hdmi_8ghz <<= 2;
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tmp_calc = hdmi_8ghz;
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do_div(tmp_calc, 6U);
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if (bclk >= HDMI_2000MHZ_BIT_CLK_HZ)
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if (bclk >= vco_range)
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return 2;
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else if (bclk >= tmp_calc)
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return 3;
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else if (bclk >= HDMI_1000MHZ_BIT_CLK_HZ)
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else if (bclk >= vco_range >> 1)
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return 4;
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tmp_calc = hdmi_8ghz;
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do_div(tmp_calc, 12U);
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if (bclk >= tmp_calc)
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return 3;
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else if (bclk >= HDMI_500MHZ_BIT_CLK_HZ)
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else if (bclk >= vco_range >> 2)
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return 4;
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tmp_calc = hdmi_8ghz;
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do_div(tmp_calc, 24U);
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if (bclk >= tmp_calc)
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return 3;
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else if (bclk >= HDMI_250MHZ_BIT_CLK_HZ)
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else if (bclk >= vco_range >> 3)
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return 4;
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return HDMI_64B_ERR_VAL;
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@ -470,15 +472,15 @@ static inline u64 hdmi_8996_v1_get_tx_band(u64 bclk)
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return HDMI_64B_ERR_VAL;
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}
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static inline u64 hdmi_8996_v2_get_tx_band(u64 bclk)
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static inline u64 hdmi_8996_v2_get_tx_band(u64 bclk, u64 vco_range)
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{
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if (bclk >= HDMI_2000MHZ_BIT_CLK_HZ)
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if (bclk >= vco_range)
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return 0;
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else if (bclk >= HDMI_1000MHZ_BIT_CLK_HZ)
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else if (bclk >= vco_range >> 1)
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return 1;
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else if (bclk >= HDMI_500MHZ_BIT_CLK_HZ)
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else if (bclk >= vco_range >> 2)
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return 2;
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else if (bclk >= HDMI_250MHZ_BIT_CLK_HZ)
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else if (bclk >= vco_range >> 3)
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return 3;
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return HDMI_64B_ERR_VAL;
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@ -498,48 +500,48 @@ static inline u64 hdmi_8996_v1_get_hsclk(u64 fdata)
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return HDMI_64B_ERR_VAL;
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}
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static inline u64 hdmi_8996_v2_get_hsclk(u64 fdata)
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static inline u64 hdmi_8996_v2_get_hsclk(u64 fdata, u64 vco_range)
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{
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u64 hdmi_2ghz = (u64)HDMI_2000MHZ_BIT_CLK_HZ;
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u64 tmp_calc = (u64)HDMI_2000MHZ_BIT_CLK_HZ;
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u64 tmp_calc = vco_range;
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tmp_calc <<= 2;
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do_div(tmp_calc, 3U);
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if (fdata >= (hdmi_2ghz << 2))
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if (fdata >= (vco_range << 2))
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return 0;
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else if (fdata >= (hdmi_2ghz << 1))
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else if (fdata >= (vco_range << 1))
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return 1;
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else if (fdata >= tmp_calc)
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return 2;
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else if (fdata >= hdmi_2ghz)
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else if (fdata >= vco_range)
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return 3;
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return HDMI_64B_ERR_VAL;
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}
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static inline u64 hdmi_8996_v2_get_vco_freq(u64 bclk)
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static inline u64 hdmi_8996_v2_get_vco_freq(u64 bclk, u64 vco_range)
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{
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u64 tx_band_div_ratio = 1U << hdmi_8996_v2_get_tx_band(bclk);
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u64 tx_band_div_ratio = 1U << hdmi_8996_v2_get_tx_band(bclk, vco_range);
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u64 pll_post_div_ratio;
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if (bclk >= HDMI_2000MHZ_BIT_CLK_HZ) {
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u64 hsclk = hdmi_8996_v2_get_hsclk(bclk);
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if (bclk >= vco_range) {
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u64 hsclk = hdmi_8996_v2_get_hsclk(bclk, vco_range);
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pll_post_div_ratio = hdmi_8996_v2_get_post_div_gt_2g(hsclk);
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} else {
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pll_post_div_ratio = hdmi_8996_v2_get_post_div_lt_2g(bclk);
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pll_post_div_ratio = hdmi_8996_v2_get_post_div_lt_2g(bclk,
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vco_range);
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}
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return bclk * (pll_post_div_ratio * tx_band_div_ratio);
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}
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static inline u64 hdmi_8996_v2_get_fdata(u64 bclk)
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static inline u64 hdmi_8996_v2_get_fdata(u64 bclk, u64 vco_range)
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{
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if (bclk >= HDMI_2000MHZ_BIT_CLK_HZ) {
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if (bclk >= vco_range) {
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return bclk;
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} else {
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u64 tmp_calc = hdmi_8996_v2_get_vco_freq(bclk);
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u64 tmp_calc = hdmi_8996_v2_get_vco_freq(bclk, vco_range);
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u64 pll_post_div_ratio_lt_2g = hdmi_8996_v2_get_post_div_lt_2g(
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bclk);
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bclk, vco_range);
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if (pll_post_div_ratio_lt_2g == HDMI_64B_ERR_VAL)
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return HDMI_64B_ERR_VAL;
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@ -885,6 +887,7 @@ static int hdmi_8996_v2_calculate(u32 pix_clk,
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u64 integloop_gain;
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u64 vco_tune;
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u64 vco_freq;
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u64 vco_range;
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u64 rem;
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/* FDATA, CLK_DIVTX, PIXEL_CLK, TMDS_CLK */
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@ -895,18 +898,21 @@ static int hdmi_8996_v2_calculate(u32 pix_clk,
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else
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tmds_clk = pix_clk;
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fdata = hdmi_8996_v2_get_fdata(bclk);
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vco_range = bclk < HDMI_282MHZ_BIT_CLK_HZ ? HDMI_2000MHZ_BIT_CLK_HZ :
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HDMI_2250MHZ_BIT_CLK_HZ;
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fdata = hdmi_8996_v2_get_fdata(bclk, vco_range);
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if (fdata == HDMI_64B_ERR_VAL)
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goto fail;
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hsclk = hdmi_8996_v2_get_hsclk(fdata);
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hsclk = hdmi_8996_v2_get_hsclk(fdata, vco_range);
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if (hsclk == HDMI_64B_ERR_VAL)
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goto fail;
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if (bclk >= HDMI_2000MHZ_BIT_CLK_HZ)
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if (bclk >= vco_range)
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post_div = hdmi_8996_v2_get_post_div_gt_2g(hsclk);
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else
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post_div = hdmi_8996_v2_get_post_div_lt_2g(bclk);
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post_div = hdmi_8996_v2_get_post_div_lt_2g(bclk, vco_range);
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if (post_div == HDMI_64B_ERR_VAL)
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goto fail;
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@ -914,13 +920,13 @@ static int hdmi_8996_v2_calculate(u32 pix_clk,
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core_clk_div = 5;
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core_clk_div_ratio = core_clk_div * 2;
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tx_band = hdmi_8996_v2_get_tx_band(bclk);
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tx_band = hdmi_8996_v2_get_tx_band(bclk, vco_range);
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if (tx_band == HDMI_64B_ERR_VAL)
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goto fail;
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tx_band_div_ratio = 1 << tx_band;
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vco_freq = hdmi_8996_v2_get_vco_freq(bclk);
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vco_freq = hdmi_8996_v2_get_vco_freq(bclk, vco_range);
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clk_divtx = vco_freq;
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do_div(clk_divtx, post_div);
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