msm: mdss: enable pll regulator during phy on sequence
Make sure pll regulator is enabled as part of the phy on sequence. This fixes some corruption observed when pll is disabled as part of the phy shut-down sequence. Change-Id: I1ace97dbf5b8e5ed8fceedddf714758a5f708cfb Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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1 changed files with 10 additions and 1 deletions
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@ -947,8 +947,11 @@ static void mdss_dsi_8996_phy_power_off(
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{
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int ln;
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void __iomem *base;
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u32 data;
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MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x7f);
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/* Turn off PLL power */
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data = MIPI_INP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0);
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MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, data & ~BIT(7));
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/* 4 lanes + clk lane configuration */
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for (ln = 0; ln < 5; ln++) {
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@ -1004,6 +1007,7 @@ static void mdss_dsi_8996_phy_power_on(
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void __iomem *base;
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struct mdss_dsi_phy_ctrl *pd;
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char *ip;
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u32 data;
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pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db);
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@ -1023,6 +1027,10 @@ static void mdss_dsi_8996_phy_power_on(
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}
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mdss_dsi_8996_phy_regulator_enable(ctrl);
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/* Turn on PLL power */
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data = MIPI_INP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0);
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MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, data | BIT(7));
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}
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static void mdss_dsi_phy_power_on(
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@ -1126,6 +1134,7 @@ static void mdss_dsi_8996_phy_config(struct mdss_dsi_ctrl_pdata *ctrl)
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mdss_dsi_8996_pll_source_standalone(ctrl);
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}
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MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x7f);
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wmb(); /* make sure registers committed */
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}
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