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iommu/arm-smmu: work around transaction hardware bug

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Work around a hardware bug where some SMMUs cache invalid PTEs and mess
up the transaction logic. PTEs must be zero'd out completely rather than
just setting the last two bits to zero to work around this bug.

Change-Id: I98ac18142eda6f7817c78ab27a4850cdecf24913
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
This commit is contained in:
Mitchel Humpherys 2014-08-12 11:03:23 -07:00 • committed by David Keitel
parent 0fd67fedf7
commit 1ac0dcf474
1 changed files with 2 additions and 0 deletions
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2
drivers/iommu/arm-smmu.c
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@ -1585,6 +1585,8 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_domain *smmu_domain,
}
do {
if (!(pteval & ARM_SMMU_PTE_PAGE))
pteval = 0;
*pte = pfn_pte(pfn, __pgprot(pteval));
} while (pte++, pfn++, addr += PAGE_SIZE, --i);
} while (addr != end);