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staging:iio:lis3l02dq: General cleanup

Browse source 
As Arnd observed, things are clearner if we pass iio_dev into read and write fucntions.

Now uses st for lis3l02dq_state everywhere.

Other bits of trivial tidying.

Signed-off-by: Jonathan Cameron <jic23@cam.ac.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Jonathan Cameron 2011-05-18 14:40:58 +01:00 • committed by Greg Kroah-Hartman
parent 3feb07979c
commit 1b076b5210
3 changed files with 84 additions and 100 deletions
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4
drivers/staging/iio/accel/lis3l02dq.h
View file

@ -173,11 +173,11 @@ struct lis3l02dq_state {
#define lis3l02dq_h_to_s(_h) \ #define lis3l02dq_h_to_s(_h) \
container_of(_h, struct lis3l02dq_state, help) container_of(_h, struct lis3l02dq_state, help)
int lis3l02dq_spi_read_reg_8(struct device *dev, int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
u8 reg_address, u8 reg_address,
u8 *val); u8 *val);
int lis3l02dq_spi_write_reg_8(struct device *dev, int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
u8 reg_address, u8 reg_address,
u8 *val); u8 *val);

118
drivers/staging/iio/accel/lis3l02dq_core.c
View file

@ -39,9 +39,17 @@
* This means that use cannot be made of spi_write etc. * This means that use cannot be made of spi_write etc.
*/ */
static int __lis3l02dq_spi_read_reg_8(struct lis3l02dq_state *st, /**
u8 reg_address, u8 *val) * lis3l02dq_spi_read_reg_8() - read single byte from a single register
* @indio_dev: iio_dev for this actual device
* @reg_address: the address of the register to be read
* @val: pass back the resulting value
**/
int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
u8 reg_address, u8 *val)
{ {
struct iio_sw_ring_helper_state *h = iio_dev_get_devdata(indio_dev);
struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
struct spi_message msg; struct spi_message msg;
int ret; int ret;
struct spi_transfer xfer = { struct spi_transfer xfer = {
@ -49,7 +57,6 @@ static int __lis3l02dq_spi_read_reg_8(struct lis3l02dq_state *st,
.rx_buf = st->rx, .rx_buf = st->rx,
.bits_per_word = 8, .bits_per_word = 8,
.len = 2, .len = 2,
.cs_change = 1,
}; };
mutex_lock(&st->buf_lock); mutex_lock(&st->buf_lock);
@ -64,50 +71,26 @@ static int __lis3l02dq_spi_read_reg_8(struct lis3l02dq_state *st,
return ret; return ret;
} }
/**
* lis3l02dq_spi_read_reg_8() - read single byte from a single register
* @dev: device asosciated with child of actual device (iio_dev or iio_trig)
* @reg_address: the address of the register to be read
* @val: pass back the resulting value
**/
int lis3l02dq_spi_read_reg_8(struct device *dev, u8 reg_address, u8 *val)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct iio_sw_ring_helper_state *h = iio_dev_get_devdata(indio_dev);
struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
return __lis3l02dq_spi_read_reg_8(st, reg_address, val);
}
/** /**
* lis3l02dq_spi_write_reg_8() - write single byte to a register * lis3l02dq_spi_write_reg_8() - write single byte to a register
* @dev: device associated with child of actual device (iio_dev or iio_trig) * @indio_dev: iio_dev for this device
* @reg_address: the address of the register to be written * @reg_address: the address of the register to be written
* @val: the value to write * @val: the value to write
**/ **/
int lis3l02dq_spi_write_reg_8(struct device *dev, int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
u8 reg_address, u8 reg_address,
u8 *val) u8 *val)
{ {
int ret; int ret;
struct spi_message msg;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct iio_sw_ring_helper_state *h struct iio_sw_ring_helper_state *h
= iio_dev_get_devdata(indio_dev); = iio_dev_get_devdata(indio_dev);
struct lis3l02dq_state *st = lis3l02dq_h_to_s(h); struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
struct spi_transfer xfer = {
.tx_buf = st->tx,
.bits_per_word = 8,
.len = 2,
.cs_change = 1,
};
mutex_lock(&st->buf_lock); mutex_lock(&st->buf_lock);
st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address); st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
st->tx[1] = *val; st->tx[1] = *val;
ret = spi_write(st->us, st->tx, 2);
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->us, &msg);
mutex_unlock(&st->buf_lock); mutex_unlock(&st->buf_lock);
return ret; return ret;
@ -115,18 +98,17 @@ int lis3l02dq_spi_write_reg_8(struct device *dev,
/** /**
* lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
* @dev: device associated with child of actual device (iio_dev or iio_trig) * @indio_dev: iio_dev for this device
* @reg_address: the address of the lower of the two registers. Second register * @lower_reg_address: the address of the lower of the two registers.
* is assumed to have address one greater. * Second register is assumed to have address one greater.
* @val: value to be written * @value: value to be written
**/ **/
static int lis3l02dq_spi_write_reg_s16(struct device *dev, static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
u8 lower_reg_address, u8 lower_reg_address,
s16 value) s16 value)
{ {
int ret; int ret;
struct spi_message msg; struct spi_message msg;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct iio_sw_ring_helper_state *h struct iio_sw_ring_helper_state *h
= iio_dev_get_devdata(indio_dev); = iio_dev_get_devdata(indio_dev);
struct lis3l02dq_state *st = lis3l02dq_h_to_s(h); struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
@ -139,7 +121,6 @@ static int lis3l02dq_spi_write_reg_s16(struct device *dev,
.tx_buf = st->tx + 2, .tx_buf = st->tx + 2,
.bits_per_word = 8, .bits_per_word = 8,
.len = 2, .len = 2,
.cs_change = 1,
}, },
}; };
@ -158,10 +139,14 @@ static int lis3l02dq_spi_write_reg_s16(struct device *dev,
return ret; return ret;
} }
static int lis3l02dq_read_16bit_s(struct lis3l02dq_state *st, static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
u8 lower_reg_address, u8 lower_reg_address,
int *val) int *val)
{ {
struct iio_sw_ring_helper_state *h
= iio_dev_get_devdata(indio_dev);
struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
struct spi_message msg; struct spi_message msg;
int ret; int ret;
s16 tempval; s16 tempval;
@ -176,7 +161,6 @@ static int lis3l02dq_read_16bit_s(struct lis3l02dq_state *st,
.rx_buf = st->rx + 2, .rx_buf = st->rx + 2,
.bits_per_word = 8, .bits_per_word = 8,
.len = 2, .len = 2,
.cs_change = 0,
}, },
}; };
@ -224,11 +208,7 @@ static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
int e, int e,
int *val) int *val)
{ {
struct iio_sw_ring_helper_state *h return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
= iio_dev_get_devdata(indio_dev);
struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
return lis3l02dq_read_16bit_s(st, LIS3L02DQ_REG_THS_L_ADDR, val);
} }
static int lis3l02dq_write_thresh(struct iio_dev *indio_dev, static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
@ -236,7 +216,7 @@ static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
int val) int val)
{ {
u16 value = val; u16 value = val;
return lis3l02dq_spi_write_reg_s16(&indio_dev->dev, return lis3l02dq_spi_write_reg_s16(indio_dev,
LIS3L02DQ_REG_THS_L_ADDR, LIS3L02DQ_REG_THS_L_ADDR,
value); value);
} }
@ -250,10 +230,8 @@ static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
u8 utemp; u8 utemp;
s8 stemp; s8 stemp;
ssize_t ret = 0; ssize_t ret = 0;
struct iio_sw_ring_helper_state *h
= iio_dev_get_devdata(indio_dev);
struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
u8 reg; u8 reg;
switch (mask) { switch (mask) {
case 0: case 0:
/* Take the iio_dev status lock */ /* Take the iio_dev status lock */
@ -265,7 +243,7 @@ static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
else { else {
reg = lis3l02dq_axis_map reg = lis3l02dq_axis_map
[LIS3L02DQ_ACCEL][chan->address]; [LIS3L02DQ_ACCEL][chan->address];
ret = lis3l02dq_read_16bit_s(st, reg, val); ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
} }
mutex_unlock(&indio_dev->mlock); mutex_unlock(&indio_dev->mlock);
return IIO_VAL_INT; return IIO_VAL_INT;
@ -275,7 +253,7 @@ static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
return IIO_VAL_INT_PLUS_MICRO; return IIO_VAL_INT_PLUS_MICRO;
case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE): case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address]; reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
ret = __lis3l02dq_spi_read_reg_8(st, reg, &utemp); ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
if (ret) if (ret)
goto error_ret; goto error_ret;
/* to match with what previous code does */ /* to match with what previous code does */
@ -284,7 +262,7 @@ static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE): case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address]; reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
ret = __lis3l02dq_spi_read_reg_8(st, reg, (u8 *)&stemp); ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
/* to match with what previous code does */ /* to match with what previous code does */
*val = stemp; *val = stemp;
return IIO_VAL_INT; return IIO_VAL_INT;
@ -297,9 +275,10 @@ static ssize_t lis3l02dq_read_frequency(struct device *dev,
struct device_attribute *attr, struct device_attribute *attr,
char *buf) char *buf)
{ {
struct iio_dev *indio_dev = dev_get_drvdata(dev);
int ret, len = 0; int ret, len = 0;
s8 t; s8 t;
ret = lis3l02dq_spi_read_reg_8(dev, ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR, LIS3L02DQ_REG_CTRL_1_ADDR,
(u8 *)&t); (u8 *)&t);
if (ret) if (ret)
@ -337,7 +316,7 @@ static ssize_t lis3l02dq_write_frequency(struct device *dev,
return ret; return ret;
mutex_lock(&indio_dev->mlock); mutex_lock(&indio_dev->mlock);
ret = lis3l02dq_spi_read_reg_8(dev, ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR, LIS3L02DQ_REG_CTRL_1_ADDR,
&t); &t);
if (ret) if (ret)
@ -362,7 +341,7 @@ static ssize_t lis3l02dq_write_frequency(struct device *dev,
goto error_ret_mutex; goto error_ret_mutex;
} }
ret = lis3l02dq_spi_write_reg_8(dev, ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR, LIS3L02DQ_REG_CTRL_1_ADDR,
&t); &t);
@ -383,7 +362,7 @@ static int lis3l02dq_initial_setup(struct lis3l02dq_state *st)
val = LIS3L02DQ_DEFAULT_CTRL1; val = LIS3L02DQ_DEFAULT_CTRL1;
/* Write suitable defaults to ctrl1 */ /* Write suitable defaults to ctrl1 */
ret = lis3l02dq_spi_write_reg_8(&st->help.indio_dev->dev, ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR, LIS3L02DQ_REG_CTRL_1_ADDR,
&val); &val);
if (ret) { if (ret) {
@ -391,7 +370,7 @@ static int lis3l02dq_initial_setup(struct lis3l02dq_state *st)
goto err_ret; goto err_ret;
} }
/* Repeat as sometimes doesn't work first time?*/ /* Repeat as sometimes doesn't work first time?*/
ret = lis3l02dq_spi_write_reg_8(&st->help.indio_dev->dev, ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR, LIS3L02DQ_REG_CTRL_1_ADDR,
&val); &val);
if (ret) { if (ret) {
@ -401,17 +380,18 @@ static int lis3l02dq_initial_setup(struct lis3l02dq_state *st)
/* Read back to check this has worked acts as loose test of correct /* Read back to check this has worked acts as loose test of correct
* chip */ * chip */
ret = lis3l02dq_spi_read_reg_8(&st->help.indio_dev->dev, ret = lis3l02dq_spi_read_reg_8(st->help.indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR, LIS3L02DQ_REG_CTRL_1_ADDR,
&valtest); &valtest);
if (ret || (valtest != val)) { if (ret || (valtest != val)) {
dev_err(&st->help.indio_dev->dev, "device not playing ball"); dev_err(&st->help.indio_dev->dev,
"device not playing ball %d %d\n", valtest, val);
ret = -EINVAL; ret = -EINVAL;
goto err_ret; goto err_ret;
} }
val = LIS3L02DQ_DEFAULT_CTRL2; val = LIS3L02DQ_DEFAULT_CTRL2;
ret = lis3l02dq_spi_write_reg_8(&st->help.indio_dev->dev, ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR, LIS3L02DQ_REG_CTRL_2_ADDR,
&val); &val);
if (ret) { if (ret) {
@ -420,7 +400,7 @@ static int lis3l02dq_initial_setup(struct lis3l02dq_state *st)
} }
val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC; val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
ret = lis3l02dq_spi_write_reg_8(&st->help.indio_dev->dev, ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR, LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
&val); &val);
if (ret) if (ret)
@ -488,7 +468,7 @@ static ssize_t lis3l02dq_read_event_config(struct iio_dev *indio_dev,
u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 + u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
(IIO_EVENT_CODE_EXTRACT_DIR(event_code) == (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
IIO_EV_DIR_RISING))); IIO_EV_DIR_RISING)));
ret = lis3l02dq_spi_read_reg_8(&indio_dev->dev, ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR, LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
&val); &val);
if (ret < 0) if (ret < 0)
@ -512,12 +492,12 @@ static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
mutex_lock(&indio_dev->mlock); mutex_lock(&indio_dev->mlock);
/* read current control */ /* read current control */
ret = lis3l02dq_spi_read_reg_8(&indio_dev->dev, ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR, LIS3L02DQ_REG_CTRL_2_ADDR,
&control); &control);
if (ret) if (ret)
goto error_ret; goto error_ret;
ret = lis3l02dq_spi_read_reg_8(&indio_dev->dev, ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR, LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
&val); &val);
if (ret < 0) if (ret < 0)
@ -537,7 +517,7 @@ static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
&indio_dev->interrupts[0]->ev_list); &indio_dev->interrupts[0]->ev_list);
} }
if (changed) { if (changed) {
ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev, ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR, LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
&val); &val);
if (ret) if (ret)
@ -545,7 +525,7 @@ static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
control = list_el->refcount ? control = list_el->refcount ?
(control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) : (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
(control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT); (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev, ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR, LIS3L02DQ_REG_CTRL_2_ADDR,
&control); &control);
} }
@ -565,7 +545,7 @@ static void lis3l02dq_thresh_handler_bh_no_check(struct work_struct *work_s)
struct lis3l02dq_state, work_thresh); struct lis3l02dq_state, work_thresh);
u8 t; u8 t;
lis3l02dq_spi_read_reg_8(&st->help.indio_dev->dev, lis3l02dq_spi_read_reg_8(st->help.indio_dev,
LIS3L02DQ_REG_WAKE_UP_SRC_ADDR, LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
&t); &t);
@ -625,7 +605,7 @@ static void lis3l02dq_thresh_handler_bh_no_check(struct work_struct *work_s)
/* reenable the irq */ /* reenable the irq */
enable_irq(st->us->irq); enable_irq(st->us->irq);
/* Ack and allow for new interrupts */ /* Ack and allow for new interrupts */
lis3l02dq_spi_read_reg_8(&st->help.indio_dev->dev, lis3l02dq_spi_read_reg_8(st->help.indio_dev,
LIS3L02DQ_REG_WAKE_UP_ACK_ADDR, LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
&t); &t);
@ -764,7 +744,7 @@ static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
u8 val = 0; u8 val = 0;
mutex_lock(&indio_dev->mlock); mutex_lock(&indio_dev->mlock);
ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev, ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR, LIS3L02DQ_REG_CTRL_1_ADDR,
&val); &val);
if (ret) { if (ret) {
@ -772,7 +752,7 @@ static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
goto err_ret; goto err_ret;
} }
ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev, ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR, LIS3L02DQ_REG_CTRL_2_ADDR,
&val); &val);
if (ret) if (ret)

62
drivers/staging/iio/accel/lis3l02dq_ring.c
View file

@ -206,7 +206,7 @@ __lis3l02dq_write_data_ready_config(struct device *dev,
struct iio_dev *indio_dev = dev_get_drvdata(dev); struct iio_dev *indio_dev = dev_get_drvdata(dev);
/* Get the current event mask register */ /* Get the current event mask register */
ret = lis3l02dq_spi_read_reg_8(dev, ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR, LIS3L02DQ_REG_CTRL_2_ADDR,
&valold); &valold);
if (ret) if (ret)
@ -220,12 +220,12 @@ __lis3l02dq_write_data_ready_config(struct device *dev,
valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION; valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
/* The double write is to overcome a hardware bug?*/ /* The double write is to overcome a hardware bug?*/
ret = lis3l02dq_spi_write_reg_8(dev, ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR, LIS3L02DQ_REG_CTRL_2_ADDR,
&valold); &valold);
if (ret) if (ret)
goto error_ret; goto error_ret;
ret = lis3l02dq_spi_write_reg_8(dev, ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR, LIS3L02DQ_REG_CTRL_2_ADDR,
&valold); &valold);
if (ret) if (ret)
@ -240,7 +240,7 @@ __lis3l02dq_write_data_ready_config(struct device *dev,
/* if not set, enable requested */ /* if not set, enable requested */
valold |= LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION; valold |= LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
iio_add_event_to_list(list, &indio_dev->interrupts[0]->ev_list); iio_add_event_to_list(list, &indio_dev->interrupts[0]->ev_list);
ret = lis3l02dq_spi_write_reg_8(dev, ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR, LIS3L02DQ_REG_CTRL_2_ADDR,
&valold); &valold);
if (ret) if (ret)
@ -275,7 +275,7 @@ static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
/* Clear any outstanding ready events */ /* Clear any outstanding ready events */
ret = lis3l02dq_read_all(st, NULL); ret = lis3l02dq_read_all(st, NULL);
} }
lis3l02dq_spi_read_reg_8(&st->help.indio_dev->dev, lis3l02dq_spi_read_reg_8(st->help.indio_dev,
LIS3L02DQ_REG_WAKE_UP_SRC_ADDR, LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
&t); &t);
return ret; return ret;
@ -328,47 +328,51 @@ static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
int lis3l02dq_probe_trigger(struct iio_dev *indio_dev) int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
{ {
int ret; int ret;
struct lis3l02dq_state *state = indio_dev->dev_data; struct iio_sw_ring_helper_state *h
= iio_dev_get_devdata(indio_dev);
struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
state->trig = iio_allocate_trigger(); st->trig = iio_allocate_trigger();
if (!state->trig) if (!st->trig)
return -ENOMEM; return -ENOMEM;
state->trig->name = kasprintf(GFP_KERNEL, st->trig->name = kasprintf(GFP_KERNEL,
"lis3l02dq-dev%d", "lis3l02dq-dev%d",
indio_dev->id); indio_dev->id);
if (!state->trig->name) { if (!st->trig->name) {
ret = -ENOMEM; ret = -ENOMEM;
goto error_free_trig; goto error_free_trig;
} }
state->trig->dev.parent = &state->us->dev; st->trig->dev.parent = &st->us->dev;
state->trig->owner = THIS_MODULE; st->trig->owner = THIS_MODULE;
state->trig->private_data = state; st->trig->private_data = st;
state->trig->set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state; st->trig->set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state;
state->trig->try_reenable = &lis3l02dq_trig_try_reen; st->trig->try_reenable = &lis3l02dq_trig_try_reen;
state->trig->control_attrs = &lis3l02dq_trigger_attr_group; st->trig->control_attrs = &lis3l02dq_trigger_attr_group;
ret = iio_trigger_register(state->trig); ret = iio_trigger_register(st->trig);
if (ret) if (ret)
goto error_free_trig_name; goto error_free_trig_name;
return 0; return 0;
error_free_trig_name: error_free_trig_name:
kfree(state->trig->name); kfree(st->trig->name);
error_free_trig: error_free_trig:
iio_free_trigger(state->trig); iio_free_trigger(st->trig);
return ret; return ret;
} }
void lis3l02dq_remove_trigger(struct iio_dev *indio_dev) void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
{ {
struct lis3l02dq_state *state = indio_dev->dev_data; struct iio_sw_ring_helper_state *h
= iio_dev_get_devdata(indio_dev);
struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
iio_trigger_unregister(state->trig); iio_trigger_unregister(st->trig);
kfree(state->trig->name); kfree(st->trig->name);
iio_free_trigger(state->trig); iio_free_trigger(st->trig);
} }
void lis3l02dq_unconfigure_ring(struct iio_dev *indio_dev) void lis3l02dq_unconfigure_ring(struct iio_dev *indio_dev)
@ -384,7 +388,7 @@ static int lis3l02dq_ring_postenable(struct iio_dev *indio_dev)
int ret; int ret;
bool oneenabled = false; bool oneenabled = false;
ret = lis3l02dq_spi_read_reg_8(&indio_dev->dev, ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR, LIS3L02DQ_REG_CTRL_1_ADDR,
&t); &t);
if (ret) if (ret)
@ -408,7 +412,7 @@ static int lis3l02dq_ring_postenable(struct iio_dev *indio_dev)
if (!oneenabled) /* what happens in this case is unknown */ if (!oneenabled) /* what happens in this case is unknown */
return -EINVAL; return -EINVAL;
ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev, ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR, LIS3L02DQ_REG_CTRL_1_ADDR,
&t); &t);
if (ret) if (ret)
@ -429,7 +433,7 @@ static int lis3l02dq_ring_predisable(struct iio_dev *indio_dev)
if (ret) if (ret)
goto error_ret; goto error_ret;
ret = lis3l02dq_spi_read_reg_8(&indio_dev->dev, ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR, LIS3L02DQ_REG_CTRL_1_ADDR,
&t); &t);
if (ret) if (ret)
@ -438,7 +442,7 @@ static int lis3l02dq_ring_predisable(struct iio_dev *indio_dev)
LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE | LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE |
LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE; LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev, ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR, LIS3L02DQ_REG_CTRL_1_ADDR,
&t); &t);