From 1ca62857bd57317b8289b31753e4ee4ce14b0e87 Mon Sep 17 00:00:00 2001 From: Alan Kwong Date: Thu, 16 Jun 2016 21:08:57 -0400 Subject: [PATCH] ARM: dts: msm: Enable v4l2 rotator node on msm8996 Enable sde v4l2 rotator node on 8996. This replaces mdss rotator node. Reserve dma 0/1, writeback mixers, writeback 0/1, and control 5 for rotator driver. Disable WFD as it shares context bank with rotator. CRs-Fixed: 1030443 Change-Id: Ie3970f29c7f1800c4457dc71a3f36a54e1cbdb91 Signed-off-by: Alan Kwong --- arch/arm/boot/dts/qcom/msm8996-mdss.dtsi | 103 ++++++++++++----------- 1 file changed, 53 insertions(+), 50 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msm8996-mdss.dtsi b/arch/arm/boot/dts/qcom/msm8996-mdss.dtsi index 5c01812d7d6e..3186f96b4275 100644 --- a/arch/arm/boot/dts/qcom/msm8996-mdss.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-mdss.dtsi @@ -14,10 +14,11 @@ mdss_mdp: qcom,mdss_mdp@900000 { compatible = "qcom,mdss_mdp"; reg = <0x00900000 0x90000>, - <0x009b0000 0x1040>, - <0x009b8000 0x1040>; - reg-names = "mdp_phys", "vbif_phys", "vbif_nrt_phys"; + <0x009b0000 0x1040>; + reg-names = "mdp_phys", "vbif_phys"; interrupts = <0 83 0>; + interrupt-controller; + #interrupt-cells = <1>; vdd-supply = <&gdsc_mdss>; #address-cells = <1>; @@ -65,12 +66,10 @@ 0x00009000 0x0000B000>; qcom,mdss-pipe-rgb-off = <0x00015000 0x00017000 0x00019000 0x0001B000>; - qcom,mdss-pipe-dma-off = <0x00025000 0x00027000>; qcom,mdss-pipe-cursor-off = <0x00035000 0x00037000>; qcom,mdss-pipe-vig-xin-id = <0 4 8 12>; qcom,mdss-pipe-rgb-xin-id = <1 5 9 13>; - qcom,mdss-pipe-dma-xin-id = <2 10>; qcom,mdss-pipe-cursor-xin-id = <7 7>; /* These Offsets are relative to "mdp_phys + mdp-reg-offset" address */ @@ -82,19 +81,16 @@ <0x2B4 4 8>, <0x2BC 4 8>, <0x2C4 4 8>; - qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>, - <0x2B4 8 12>; qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3A8 16 15>, <0x3B0 16 15>; qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400 - 0x00002600 0x00002800>; + 0x00002600>; qcom,mdss-mixer-intf-off = <0x00045000 0x00046000 0x00047000 0x0004A000>; - qcom,mdss-mixer-wb-off = <0x00048000 0x00049000>; qcom,mdss-dspp-off = <0x00055000 0x00057000>; - qcom,mdss-wb-off = <0x00065000 0x00065800 0x00066000>; + qcom,mdss-wb-off = <0x00066000>; qcom,mdss-intf-off = <0x0006B000 0x0006B800 0x0006C000 0x0006C800>; qcom,mdss-pingpong-off = <0x00071000 0x00071800 @@ -103,6 +99,7 @@ qcom,mdss-ppb-ctl-off = <0x00000330 0x00000338>; qcom,mdss-ppb-cfg-off = <0x00000334 0x0000033C>; qcom,mdss-has-pingpong-split; + qcom,mdss-has-separate-rotator; qcom,mdss-ad-off = <0x0079000 0x00079800 0x0007a000>; qcom,mdss-cdm-off = <0x0007a200>; @@ -111,7 +108,6 @@ qcom,mdss-has-source-split; qcom,mdss-highest-bank-bit = <0x2>; qcom,mdss-has-decimation; - qcom,mdss-has-rotator-downscale; qcom,mdss-idle-power-collapse-enabled; clocks = <&clock_mmss clk_mdss_ahb_clk>, <&clock_mmss clk_mdss_axi_clk>, @@ -248,19 +244,6 @@ "mdp_axi_clk"; }; - smmu_rot_unsec: qcom,smmu_rot_unsec_cb { - compatible = "qcom,smmu_rot_unsec"; - iommus = <&rot_smmu 0>; - reg = <0x00d09000 0xd00>; - reg-names = "mmu_cb"; - gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; - clocks = <&clock_mmss clk_smmu_rot_ahb_clk>, - <&clock_mmss clk_mmagic_mdss_axi_clk>, - <&clock_mmss clk_smmu_rot_axi_clk>; - clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk", - "rot_axi_clk"; - }; - smmu_mdp_sec: qcom,smmu_mdp_sec_cb { compatible = "qcom,smmu_mdp_sec"; iommus = <&mdp_smmu 1>; @@ -274,19 +257,6 @@ "mdp_axi_clk"; }; - smmu_rot_sec: qcom,smmu_rot_sec_cb { - compatible = "qcom,smmu_rot_sec"; - iommus = <&rot_smmu 1>; - reg = <0x00d0b000 0xd00>; - reg-names = "mmu_cb"; - gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; - clocks = <&clock_mmss clk_smmu_rot_ahb_clk>, - <&clock_mmss clk_mmagic_mdss_axi_clk>, - <&clock_mmss clk_smmu_rot_axi_clk>; - clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk", - "rot_axi_clk"; - }; - mdss_fb0: qcom,mdss_fb_primary { cell-index = <0>; compatible = "qcom,mdss-fb"; @@ -295,11 +265,6 @@ }; }; - mdss_fb1: qcom,mdss_fb_wfd { - cell-index = <1>; - compatible = "qcom,mdss-fb"; - }; - mdss_fb2: qcom,mdss_fb_hdmi { cell-index = <2>; compatible = "qcom,mdss-fb"; @@ -492,7 +457,6 @@ compatible = "qcom,mdss_wb"; qcom,mdss_pan_res = <640 480>; qcom,mdss_pan_bpp = <24>; - qcom,mdss-fb-map = <&mdss_fb1>; }; mdss_hdmi_tx: qcom,hdmi_tx@9a0000 { @@ -530,11 +494,15 @@ }; mdss_rotator: qcom,mdss_rotator { - compatible = "qcom,mdss_rotator"; - qcom,mdss-wb-count = <2>; - qcom,mdss-has-downscale; - qcom,mdss-has-ubwc; - qcom,mdss-has-reg-bus; + compatible = "qcom,sde_rotator"; + reg = <0x00900000 0x90000>, + <0x009b8000 0x1040>; + reg-names = "mdp_phys", + "rot_vbif_phys"; + qcom,mdss-wb-count = <1>; + qcom,mdss-wb-id = <0>; + qcom,mdss-ctl-id = <4>; + qcom,mdss-highest-bank-bit = <0x2>; /* Bus Scale Settings */ qcom,msm-bus,name = "mdss_rotator"; qcom,msm-bus,num-cases = <3>; @@ -550,7 +518,42 @@ qcom,supply-names = "rot-mmagic-mdss-gdsc", "rot-vdd"; clocks = <&clock_mmss clk_mmss_misc_ahb_clk>, - <&clock_mmss clk_mdss_rotator_vote_clk>; - clock-names = "iface_clk", "rot_core_clk"; + <&clock_mmss clk_mdss_rotator_vote_clk>, + <&clock_mmss clk_mdss_ahb_clk>, + <&clock_mmss clk_mdss_axi_clk>, + <&clock_mmss clk_mdp_clk_src>; + clock-names = "iface_clk", "rot_core_clk", + "mdss_ahb_clk", "mdss_axi_clk", "mdp_clk_src"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <32 0>; + + /* VBIF QoS remapper settings*/ + qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <16>; + + smmu_rot_unsecure: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&rot_smmu 0>; + gdsc-mdss-supply = <&gdsc_mmagic_mdss>; + clocks = <&clock_mmss clk_smmu_rot_ahb_clk>, + <&clock_mmss clk_mmagic_mdss_axi_clk>, + <&clock_mmss clk_smmu_rot_axi_clk>; + clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk", + "rot_axi_clk"; + }; + + smmu_rot_secure: qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <&rot_smmu 1>; + gdsc-mdss-supply = <&gdsc_mmagic_mdss>; + clocks = <&clock_mmss clk_smmu_rot_ahb_clk>, + <&clock_mmss clk_mmagic_mdss_axi_clk>, + <&clock_mmss clk_smmu_rot_axi_clk>; + clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk", + "rot_axi_clk"; + }; }; };