evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

msm: mdss: dsi: update DSI phy v3 initialization sequence

Browse source 
Update the DSI phy v3 initialization sequence as per the
recommended values. The key changes include deferring the
enabling of the global bit clock until after the PLL is
locked, along with updates to the lane strength settings.

CRs-Fixed: 1033911
Change-Id: I1993f5cedb629f44a5b07d429a77f17218f2d6e7
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
This commit is contained in:
Aravind Venkateswaran 2016-08-17 12:00:34 -07:00
parent bd1ead72ec
commit 1df0ae65ac
1 changed files with 9 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
drivers/video/fbdev/msm/mdss_dsi_phy_v3.c
View file

@ -113,8 +113,8 @@ static void mdss_dsi_phy_v3_set_pll_source(
else
pll_src = 0x00; /* internal PLL */
/* set the PLL src and set global clock enable */
reg = (pll_src << 2) | BIT(5);
/* set the PLL src */
reg = (pll_src << 2);
DSI_PHY_W32(ctrl->phy_io.base, CMN_CLK_CFG1, reg);
}
@ -183,7 +183,7 @@ static void mdss_dsi_phy_v3_config_lane_settings(
struct mdss_dsi_ctrl_pdata *ctrl)
{
int i;
u32 tx_dctrl[] = {0x98, 0x99, 0x98, 0x9a, 0x98};
u32 tx_dctrl[] = {0x18, 0x19, 0x18, 0x02, 0x18};
struct mdss_dsi_phy_ctrl *pd =
&(((ctrl->panel_data).panel_info.mipi).dsi_phy_db);
@ -198,8 +198,8 @@ static void mdss_dsi_phy_v3_config_lane_settings(
*/
DSI_PHY_W32(ctrl->phy_io.base, LNX_LPRX_CTRL(i), 0);
DSI_PHY_W32(ctrl->phy_io.base, LNX_HSTX_STR_CTRL(i), 0x88);
DSI_PHY_W32(ctrl->phy_io.base, LNX_PIN_SWAP(i), 0x0);
DSI_PHY_W32(ctrl->phy_io.base, LNX_HSTX_STR_CTRL(i), 0x88);
}
mdss_dsi_phy_v3_config_lpcdrx(ctrl, true);
@ -383,8 +383,11 @@ int mdss_dsi_phy_v3_init(struct mdss_dsi_ctrl_pdata *ctrl,
return rc;
}
/* de-assert digital power down */
DSI_PHY_W32(ctrl->phy_io.base, CMN_CTRL_0, BIT(6));
/* de-assert digital and pll power down */
DSI_PHY_W32(ctrl->phy_io.base, CMN_CTRL_0, BIT(6) | BIT(5));
/* Assert PLL core reset */
DSI_PHY_W32(ctrl->phy_io.base, CMN_PLL_CNTRL, 0x00);
/* turn off resync FIFO */
DSI_PHY_W32(ctrl->phy_io.base, CMN_RBUF_CTRL, 0x00);