evie/android_kernel_oneplus_msm8998
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msm: mdss: update clamp ctrl register config for msm8996

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Clamp control enable register is different on 8996 target.
Update DSI software to handle it based on DSI version.

Change-Id: Iac61ac0a03397633154d2fe1bf44bcaaeeab1c52
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This commit is contained in:
Kuogee Hsieh 2015-03-03 17:19:26 -08:00 • committed by David Keitel
parent 9086f7ef89
commit 1e32b0c2e8
2 changed files with 39 additions and 20 deletions
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15
drivers/video/fbdev/msm/mdss_dsi.c
View file

@ -1881,16 +1881,17 @@ int dsi_panel_device_register(struct device_node *pan_node,
rc = of_property_read_u32(ctrl_pdev->dev.of_node, rc = of_property_read_u32(ctrl_pdev->dev.of_node,
"qcom,mmss-ulp-clamp-ctrl-offset", "qcom,mmss-ulp-clamp-ctrl-offset",
&ctrl_pdata->ulps_clamp_ctrl_off); &ctrl_pdata->ulps_clamp_ctrl_off);
if (!rc) { if (rc && pinfo->mipi.mode == DSI_CMD_MODE) {
rc = of_property_read_u32(ctrl_pdev->dev.of_node, pr_err("%s: dsi clamp register settings missing\n",
"qcom,mmss-phyreset-ctrl-offset",
&ctrl_pdata->ulps_phyrst_ctrl_off);
}
if (rc && pinfo->ulps_feature_enabled) {
pr_err("%s: dsi ulps clamp register settings missing\n",
__func__); __func__);
return -EINVAL; return -EINVAL;
} }
rc = of_property_read_u32(ctrl_pdev->dev.of_node,
"qcom,mmss-phyreset-ctrl-offset",
&ctrl_pdata->ulps_phyrst_ctrl_off);
if (rc && pinfo->mipi.mode == DSI_CMD_MODE)
pr_debug("%s: dsi phyreset register settings missing\n",
__func__);
ctrl_pdata->cmd_sync_wait_broadcast = of_property_read_bool( ctrl_pdata->cmd_sync_wait_broadcast = of_property_read_bool(
pan_node, "qcom,cmd-sync-wait-broadcast"); pan_node, "qcom,cmd-sync-wait-broadcast");

44
drivers/video/fbdev/msm/msm_mdss_io_8974.c
View file

@ -1319,7 +1319,7 @@ static int mdss_dsi_clamp_ctrl(struct mdss_dsi_ctrl_pdata *ctrl, int enable)
} }
if (!ctrl->mmss_misc_io.base) { if (!ctrl->mmss_misc_io.base) {
pr_err("%s: mmss_misc_io not mapped\nn", __func__); pr_err("%s: mmss_misc_io not mapped\n", __func__);
return -EINVAL; return -EINVAL;
} }
@ -1355,44 +1355,62 @@ static int mdss_dsi_clamp_ctrl(struct mdss_dsi_ctrl_pdata *ctrl, int enable)
pr_debug("%s: called for ctrl%d, enable=%d, clamp_reg=0x%08x\n", pr_debug("%s: called for ctrl%d, enable=%d, clamp_reg=0x%08x\n",
__func__, ctrl->ndx, enable, clamp_reg); __func__, ctrl->ndx, enable, clamp_reg);
if (enable && !ctrl->mmss_clamp) { if (enable && !ctrl->mmss_clamp) {
regval = MIPI_INP(ctrl->mmss_misc_io.base + clamp_reg_off);
/* Enable MMSS DSI Clamps */ /* Enable MMSS DSI Clamps */
if (ctrl->ndx == DSI_CTRL_0) { if (ctrl->ndx == DSI_CTRL_0) {
regval = MIPI_INP(ctrl->mmss_misc_io.base +
clamp_reg_off);
MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off,
regval | clamp_reg); regval | clamp_reg);
MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off,
regval | (clamp_reg | BIT(15))); regval | (clamp_reg | BIT(15)));
} else if (ctrl->ndx == DSI_CTRL_1) { } else if (ctrl->ndx == DSI_CTRL_1) {
regval = MIPI_INP(ctrl->mmss_misc_io.base +
clamp_reg_off);
MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off,
regval | (clamp_reg << 16)); regval | (clamp_reg << 16));
MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off,
regval | ((clamp_reg << 16) | BIT(31))); regval | ((clamp_reg << 16) | BIT(31)));
} }
/* update clamp ctrl before setting phy reset disable */
wmb();
/* /*
* This register write ensures that DSI PHY will not be * This register write ensures that DSI PHY will not be
* reset when mdss ahb clock reset is asserted while coming * reset when mdss ahb clock reset is asserted while coming
* out of power collapse * out of power collapse
*/ */
MIPI_OUTP(ctrl->mmss_misc_io.base + phyrst_reg_off, 0x1); if (ctrl->hw_rev == MDSS_DSI_HW_REV_104) {
regval = MIPI_INP(ctrl->mmss_misc_io.base +
clamp_reg_off);
MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off,
regval | BIT(30));
} else {
MIPI_OUTP(ctrl->mmss_misc_io.base + phyrst_reg_off,
0x1);
}
/* make sure that clamp ctrl is updated before disable call */
wmb();
ctrl->mmss_clamp = true; ctrl->mmss_clamp = true;
} else if (!enable && ctrl->mmss_clamp) { } else if (!enable && ctrl->mmss_clamp) {
MIPI_OUTP(ctrl->mmss_misc_io.base + phyrst_reg_off, 0x0); if (ctrl->hw_rev == MDSS_DSI_HW_REV_104) {
/* Disable MMSS DSI Clamps */
if (ctrl->ndx == DSI_CTRL_0) {
regval = MIPI_INP(ctrl->mmss_misc_io.base + regval = MIPI_INP(ctrl->mmss_misc_io.base +
clamp_reg_off); clamp_reg_off);
MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off,
regval & ~BIT(30));
} else {
MIPI_OUTP(ctrl->mmss_misc_io.base + phyrst_reg_off,
0x0);
}
/* update clamp ctrl before unsetting phy reset disable */
wmb();
regval = MIPI_INP(ctrl->mmss_misc_io.base + clamp_reg_off);
/* Disable MMSS DSI Clamps */
if (ctrl->ndx == DSI_CTRL_0)
MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off,
regval & ~(clamp_reg | BIT(15))); regval & ~(clamp_reg | BIT(15)));
} else if (ctrl->ndx == DSI_CTRL_1) { else if (ctrl->ndx == DSI_CTRL_1)
regval = MIPI_INP(ctrl->mmss_misc_io.base +
clamp_reg_off);
MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off,
regval & ~((clamp_reg << 16) | BIT(31))); regval & ~((clamp_reg << 16) | BIT(31)));
} /* make sure that clamp ctrl is updated before enable call */
wmb();
ctrl->mmss_clamp = false; ctrl->mmss_clamp = false;
} else { } else {
pr_debug("%s: No change requested: %s -> %s\n", __func__, pr_debug("%s: No change requested: %s -> %s\n", __func__,