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msm: ep_pcie: add the phy reset clock

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Add the phy reset clock for PCIe endpoint mode and add the support
of this optional clock.

Change-Id: Id92e2fd589d0e97e8a3db2e1eeb1d6c99a464777
Signed-off-by: Yan He <yanhe@codeaurora.org>
This commit is contained in:
Yan He 2015-05-29 17:46:23 -07:00 • committed by David Keitel
parent ce12d18898
commit 1e5604cf01
2 changed files with 5 additions and 5 deletions
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2
drivers/platform/msm/ep_pcie/ep_pcie_com.h
View file

@ -109,7 +109,7 @@
#define EP_PCIE_LOG_PAGES 50
#define EP_PCIE_MAX_VREG 2
#define EP_PCIE_MAX_CLK 5
#define EP_PCIE_MAX_CLK 6
#define EP_PCIE_MAX_PIPE_CLK 1
#define EP_PCIE_ERROR -30655

8
drivers/platform/msm/ep_pcie/ep_pcie_core.c
View file

@ -66,7 +66,8 @@ static struct ep_pcie_clk_info_t
{NULL, "pcie_0_mstr_axi_clk", 0, true},
{NULL, "pcie_0_slv_axi_clk", 0, true},
{NULL, "pcie_0_aux_clk", 1000000, true},
{NULL, "pcie_0_ldo", 0, true}
{NULL, "pcie_0_ldo", 0, true},
{NULL, "pcie_0_phy_reset", 0, false}
};
static struct ep_pcie_clk_info_t
@ -286,11 +287,10 @@ static int ep_pcie_clk_init(struct ep_pcie_dev_t *dev)
info = &dev->clk[i];
if (!info->hdl) {
EP_PCIE_ERR(dev,
EP_PCIE_DBG(dev,
"PCIe V%d: handle of Clock %s is NULL\n",
dev->rev, info->name);
rc = -EINVAL;
break;
continue;
}
if (info->freq) {