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Merge "clk: msm: mdss: fix divider configuration for 5.4 Ghz link rate"

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Linux Build Service Account 2016-11-14 21:53:58 -08:00 • committed by Gerrit - the friendly Code Review server
commit 1f3e1e0986
1 changed files with 1 additions and 1 deletions
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drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c
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@ -275,7 +275,7 @@ int dp_config_vco_rate(struct dp_pll_vco_clk *vco, unsigned long rate)
MDSS_PLL_REG_W(dp_res->pll_base,
QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00);
MDSS_PLL_REG_W(dp_res->pll_base,
QSERDES_COM_DIV_FRAC_START3_MODE0, 0xa0);
QSERDES_COM_DIV_FRAC_START3_MODE0, 0x0a);
MDSS_PLL_REG_W(dp_res->pll_base,
QSERDES_COM_CMN_CONFIG, 0x12);
MDSS_PLL_REG_W(dp_res->pll_base,