From 1fdef7ce530009a509815ffcfbf108bc57a4de92 Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Thu, 8 Sep 2016 11:09:37 -0700 Subject: [PATCH] dwc3: core: clear DELAYP1TRANS with USB3PIPECTL register Commit fd115e68971b ("dwc3: core: Don't perform controller and PHYs soft reset") removed clearing DELAYP1TRANS. It is recommended to clear DELAYP1TRANS bit with USB3PIPECTL register which controls USB controller allowing USB QMP PHY low power transitions. Change-Id: I54ba694f4c997bf5ecc540cee274e2cb07b77446 Signed-off-by: Mayank Rana --- drivers/usb/dwc3/core.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 7585c603cb3d..9fb05bbf3e74 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -155,6 +155,7 @@ static int dwc3_init_usb_phys(struct dwc3 *dwc) static int dwc3_core_reset(struct dwc3 *dwc) { int ret; + u32 reg; /* Reset PHYs */ usb_phy_reset(dwc->usb2_phy); @@ -168,6 +169,10 @@ static int dwc3_core_reset(struct dwc3 *dwc) return ret; } + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + reg &= ~DWC3_GUSB3PIPECTL_DELAYP1TRANS; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + dwc3_notify_event(dwc, DWC3_CONTROLLER_RESET_EVENT); dwc3_notify_event(dwc, DWC3_CONTROLLER_POST_RESET_EVENT);