mmc: host: sdhci-msm: Skip reading GENERICS register in check_pwr_status
Skip checking the SWITCHABLE_SIGNALING_VOLTAGE bit of MCI_GENERICS register while checking power status on SDHC v5.0 onwards. This bit shows whether controller supports switching of IO signaling voltage or not. On SDHC v5.0, switchable signaling voltage support is present by default and this bit was removed. So we can skip checking this bit in case of v5.0 controller. Without this patch, driver tries to read a non-existing bit field which is causing driver to proceed without waiting for pwr-irq. In some case its turning off the clock even before pwr irq finishes thus resulting in un-clocked access errors. Change-Id: I5beaf5bf043999522e3f2ec537568524c5aec4bf Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
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1 changed files with 4 additions and 3 deletions
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@ -2736,14 +2736,15 @@ static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
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msm_host->offset;
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unsigned long flags;
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bool done = false;
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u32 io_sig_sts;
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u32 io_sig_sts = SWITCHABLE_SIGNALLING_VOL;
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spin_lock_irqsave(&host->lock, flags);
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pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
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mmc_hostname(host->mmc), __func__, req_type,
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msm_host->curr_pwr_state, msm_host->curr_io_level);
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io_sig_sts = sdhci_msm_readl_relaxed(host,
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msm_host_offset->CORE_GENERICS);
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if (!msm_host->mci_removed)
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io_sig_sts = sdhci_msm_readl_relaxed(host,
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msm_host_offset->CORE_GENERICS);
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/*
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* The IRQ for request type IO High/Low will be generated when -
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