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mdss: display-port: fix register offsets for link training

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Add proper register base and register address offsets
when configuring the voltage swings and preemphsis
settings. Fix interrupt register bit for VIDEO_READY.

Change-Id: I6e89f6fbb3660d13c186b38eb7ca1f71cbe8109d
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
This commit is contained in:
Chandan Uddaraju 2016-07-20 14:37:58 -07:00 • committed by Gerrit - the friendly Code Review server
parent f34448c324
commit 20f40d92b8
3 changed files with 56 additions and 34 deletions
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17
drivers/video/fbdev/msm/mdss_dp.h
View file

@ -103,10 +103,6 @@
#define EDP_INTR_MASK2 (EDP_INTR_STATUS2 << 2)
#define EDP_PHY_EDPPHY_GLB_VM_CFG0 0x510
#define EDP_PHY_EDPPHY_GLB_VM_CFG1 0x514
struct edp_cmd {
char read; /* 1 == read, 0 == write */
char i2c; /* 1 == i2c cmd, 0 == native cmd */
@ -148,15 +144,16 @@ enum dp_pm_type {
#define EV_IDLE_PATTERNS_SENT BIT(30)
#define EV_VIDEO_READY BIT(31)
/* edp state ctrl */
/* dp state ctrl */
#define ST_TRAIN_PATTERN_1 BIT(0)
#define ST_TRAIN_PATTERN_2 BIT(1)
#define ST_TRAIN_PATTERN_3 BIT(2)
#define ST_SYMBOL_ERR_RATE_MEASUREMENT BIT(3)
#define ST_PRBS7 BIT(4)
#define ST_CUSTOM_80_BIT_PATTERN BIT(5)
#define ST_SEND_VIDEO BIT(6)
#define ST_PUSH_IDLE BIT(7)
#define ST_TRAIN_PATTERN_4 BIT(3)
#define ST_SYMBOL_ERR_RATE_MEASUREMENT BIT(4)
#define ST_PRBS7 BIT(5)
#define ST_CUSTOM_80_BIT_PATTERN BIT(6)
#define ST_SEND_VIDEO BIT(7)
#define ST_PUSH_IDLE BIT(8)
/* sink power state */
#define SINK_POWER_ON 1

66
drivers/video/fbdev/msm/mdss_dp_aux.c
View file

@ -1037,23 +1037,37 @@ char vm_voltage_swing[4][4] = {
{0x1E, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */
};
static void dp_voltage_pre_emphasise_set(struct mdss_dp_drv_pdata *ep)
static void dp_voltage_pre_emphasise_set(struct mdss_dp_drv_pdata *dp)
{
u32 value0 = 0;
u32 value1 = 0;
pr_debug("v=%d p=%d\n", ep->v_level, ep->p_level);
pr_debug("v=%d p=%d\n", dp->v_level, dp->p_level);
value0 = vm_pre_emphasis[(int)(ep->v_level)][(int)(ep->p_level)];
value1 = vm_voltage_swing[(int)(ep->v_level)][(int)(ep->p_level)];
value0 = vm_voltage_swing[(int)(dp->v_level)][(int)(dp->p_level)];
value1 = vm_pre_emphasis[(int)(dp->v_level)][(int)(dp->p_level)];
/* Enable MUX to use Cursor values from these registers */
value0 |= BIT(5);
value1 |= BIT(5);
/* Configure host and panel only if both values are allowed */
if (value0 != 0xFF && value1 != 0xFF) {
dp_write(ep->base + EDP_PHY_EDPPHY_GLB_VM_CFG0, value0);
dp_write(ep->base + EDP_PHY_EDPPHY_GLB_VM_CFG1, value1);
dp_write(dp->phy_io.base +
QSERDES_TX0_OFFSET + TXn_TX_DRV_LVL,
value0);
dp_write(dp->phy_io.base +
QSERDES_TX1_OFFSET + TXn_TX_DRV_LVL,
value0);
dp_write(dp->phy_io.base +
QSERDES_TX0_OFFSET + TXn_TX_EMP_POST1_LVL,
value1);
dp_write(dp->phy_io.base +
QSERDES_TX1_OFFSET + TXn_TX_EMP_POST1_LVL,
value1);
pr_debug("value0=0x%x value1=0x%x",
value0, value1);
dp_lane_set_write(ep, ep->v_level, ep->p_level);
dp_lane_set_write(dp, dp->v_level, dp->p_level);
}
}
@ -1212,34 +1226,36 @@ static void dp_clear_training_pattern(struct mdss_dp_drv_pdata *ep)
usleep_range(usleep_time, usleep_time);
}
static int dp_aux_link_train(struct mdss_dp_drv_pdata *ep)
static int dp_aux_link_train(struct mdss_dp_drv_pdata *dp)
{
int ret = 0;
int usleep_time;
ret = dp_aux_chan_ready(ep);
ret = dp_aux_chan_ready(dp);
if (ret) {
pr_err("LINK Train failed: aux chan NOT ready\n");
complete(&ep->train_comp);
complete(&dp->train_comp);
return ret;
}
dp_write(ep->base + DP_MAINLINK_CTRL, 0x1);
dp_write(dp->base + DP_MAINLINK_CTRL, 0x1);
mdss_dp_sink_power_state(ep, SINK_POWER_ON);
mdss_dp_sink_power_state(dp, SINK_POWER_ON);
train_start:
ep->v_level = 0; /* start from default level */
ep->p_level = 0;
dp_cap_lane_rate_set(ep);
dp->v_level = 0; /* start from default level */
dp->p_level = 0;
dp_cap_lane_rate_set(dp);
mdss_dp_config_ctrl(dp);
dp_clear_training_pattern(ep);
usleep_time = ep->dpcd.training_read_interval;
mdss_dp_state_ctrl(&dp->ctrl_io, 0);
dp_clear_training_pattern(dp);
usleep_time = dp->dpcd.training_read_interval;
usleep_range(usleep_time, usleep_time);
ret = dp_start_link_train_1(ep);
ret = dp_start_link_train_1(dp);
if (ret < 0) {
if (dp_link_rate_down_shift(ep) == 0) {
if (dp_link_rate_down_shift(dp) == 0) {
goto train_start;
} else {
pr_err("Training 1 failed\n");
@ -1250,10 +1266,11 @@ train_start:
pr_debug("Training 1 completed successfully\n");
dp_clear_training_pattern(ep);
ret = dp_start_link_train_2(ep);
mdss_dp_state_ctrl(&dp->ctrl_io, 0);
dp_clear_training_pattern(dp);
ret = dp_start_link_train_2(dp);
if (ret < 0) {
if (dp_link_rate_down_shift(ep) == 0) {
if (dp_link_rate_down_shift(dp) == 0) {
goto train_start;
} else {
pr_err("Training 2 failed\n");
@ -1264,10 +1281,11 @@ train_start:
pr_debug("Training 2 completed successfully\n");
mdss_dp_state_ctrl(&dp->ctrl_io, ST_SEND_VIDEO);
clear:
dp_clear_training_pattern(ep);
dp_clear_training_pattern(dp);
complete(&ep->train_comp);
complete(&dp->train_comp);
return ret;
}

7
drivers/video/fbdev/msm/mdss_dp_util.h
View file

@ -76,6 +76,12 @@
#define DP_PHY_AUX_INTERRUPT_MASK (0x00000044)
#define DP_PHY_AUX_INTERRUPT_CLEAR (0x00000048)
#define QSERDES_TX0_OFFSET 0x0400
#define QSERDES_TX1_OFFSET 0x0800
#define TXn_TX_EMP_POST1_LVL 0x000C
#define TXn_TX_DRV_LVL 0x001C
#define TCSR_USB3_DP_PHYMODE 0x48
struct lane_mapping {
@ -85,6 +91,7 @@ struct lane_mapping {
char lane3;
};
void mdss_dp_state_ctrl(struct dss_io_data *ctrl_io, u32 data);
u32 mdss_dp_get_ctrl_hw_version(struct dss_io_data *ctrl_io);
u32 mdss_dp_get_phy_hw_version(struct dss_io_data *phy_io);
void mdss_dp_aux_reset(struct dss_io_data *ctrl_io);