From f795f9a639c668e20d55e8e27a21845810d5c200 Mon Sep 17 00:00:00 2001 From: Venkat Gopalakrishnan Date: Wed, 31 Aug 2016 17:37:45 -0700 Subject: [PATCH] ARM: dts: msm: enable aggre1 ufs hw ctl clock for msmcobalt QCOM UFS host controller v3.0.0 supports hw gating of clocks, enable the use of hw ctl clock variant of aggre1 ufs clock. Change-Id: I3f0e718362a73c2c440fa2b0aea816fa058fdaa3 Signed-off-by: Venkat Gopalakrishnan --- arch/arm/boot/dts/qcom/msmcobalt.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 007966a1e52f..8e5621e5716a 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -1697,7 +1697,7 @@ "rx_lane0_sync_clk"; clocks = <&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>, - <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_hw_ctl_clk>, <&clock_gcc clk_gcc_ufs_ahb_clk>, <&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>, <&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>,