ARM: dts: msm: Add msm-core device for msmfalcon
Add msm-core device to run power and temperature calculation on the cores. Change-Id: I3e8300f15757739714579055985e3fff1a4d8f86 Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
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1 changed files with 47 additions and 0 deletions
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@ -48,6 +48,7 @@
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reg = <0x0 0x0>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile0>;
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qcom,ea = <&ea0>;
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};
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CPU1: cpu@1 {
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@ -56,6 +57,7 @@
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reg = <0x0 0x1>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile0>;
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qcom,ea = <&ea1>;
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};
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CPU2: cpu@2 {
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@ -64,6 +66,7 @@
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reg = <0x0 0x2>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile0>;
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qcom,ea = <&ea2>;
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};
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CPU3: cpu@3 {
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@ -72,6 +75,7 @@
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reg = <0x0 0x3>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile0>;
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qcom,ea = <&ea3>;
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};
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CPU4: cpu@100 {
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@ -80,6 +84,7 @@
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reg = <0x0 0x100>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile1>;
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qcom,ea = <&ea4>;
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};
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CPU5: cpu@101 {
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@ -88,6 +93,7 @@
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reg = <0x0 0x101>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile2>;
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qcom,ea = <&ea5>;
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};
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CPU6: cpu@102 {
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@ -96,6 +102,7 @@
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reg = <0x0 0x102>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile3>;
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qcom,ea = <&ea6>;
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};
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CPU7: cpu@103 {
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@ -104,6 +111,7 @@
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reg = <0x0 0x103>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile4>;
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qcom,ea = <&ea7>;
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};
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cpu-map {
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@ -540,6 +548,45 @@
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};
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};
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qcom,msm-core@780000 {
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compatible = "qcom,apss-core-ea";
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reg = <0x780000 0x1000>;
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qcom,low-hyst-temp = <10>;
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qcom,high-hyst-temp = <5>;
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ea0: ea0 {
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sensor = <&sensor_information1>;
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};
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ea1: ea1 {
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sensor = <&sensor_information1>;
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};
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ea2: ea2 {
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sensor = <&sensor_information1>;
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};
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ea3: ea3 {
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sensor = <&sensor_information1>;
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};
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ea4: ea4 {
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sensor = <&sensor_information3>;
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};
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ea5: ea5 {
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sensor = <&sensor_information4>;
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};
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ea6: ea6 {
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sensor = <&sensor_information5>;
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};
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ea7: ea7 {
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sensor = <&sensor_information6>;
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};
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};
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uartblsp2dm1: serial@0c1b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xc1b0000 0x1000>;
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